PIC12F635T-I/MD Microchip Technology, PIC12F635T-I/MD Datasheet - Page 26
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PIC12F635T-I/MD
Manufacturer Part Number
PIC12F635T-I/MD
Description
1.75 KB Flash, 64 RAM, 6 I/O 8 DFN 4x4mm T/R
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Specifications of PIC12F635T-I/MD
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
5
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164326 - MODULA SKT PM3 20QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFNXLT08DFN - SOCKET TRANSITION ICE 8DFN
Data Converters
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC12F635/PIC16F636/639
TABLE 2-4:
DS41232D-page 24
Addr
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah PCLATH
8Bh INTCON
8Ch PIE1
8Dh
8Eh PCON
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
9Bh
99h
9Ah EEDAT
9Bh EEADR
9Ch EECON1
9Dh EECON2
9Eh
9Fh
Legend:
Note 1:
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISC
OSCCON
OSCTUNE
LVDCON
WPUDA
IOCA
WDA
VRCON
2:
3:
Name
(2)
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
RA3 pull-up is enabled when pin is configured as MCLR in the Configuration Word register.
MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set
again if the mismatch exists.
—
—
—
—
—
—
—
—
—
—
(2)
PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addressing this location uses contents of FSR to address data memory
(not a physical register)
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
EEPROM Control Register 2 (not a physical register)
Unimplemented
Unimplemented
EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000
RAPU
VREN
EEIE
Bit 7
GIE
IRP
—
—
—
—
—
—
—
—
—
—
—
INTEDG
IRCF2
LVDIE
PEIE
Bit 6
RP1
—
—
—
—
—
—
—
—
—
—
—
ULPWUE SBOREN
WPUDA5 WPUDA4
TRISA5
TRISC5
IRCF1
IRVST
IOCA5
WDA5
T0CS
CRIE
Bit 5
T0IE
VRR
RP0
—
—
—
Write Buffer for upper 5 bits of Program Counter
TRISC4
TRISA4
LVDEN
IOCA4
IRCF0
WDA4
T0SE
TUN4
INTE
C2IE
Bit 4
TO
—
—
WRERR
TRISA3
TRISC3
IOCA3
OSTS
TUN3
RAIE
WUR
Bit 3
C1IE
PSA
VR3
PD
—
—
—
WPUDA2 WPUDA1 WPUDA0 --11 -111 --11 -111
TRISA2
TRISC2
OSFIE
LVDL2
IOCA2
WREN
WDA2
TUN2
Bit 2
T0IF
PS2
HTS
VR2
—
Z
TRISA1
TRISC1
LVDL1
IOCA1
WDA1
TUN1
Bit 1
INTF
POR
VR1
PS1
LTS
WR
DC
—
TMR1IE 0000 00-0
TRISA0 --11 1111 --11 1111
TRISC0 --11 1111 --11 1111
RAIF
LVDL0
IOCA0
WDA0
TUN0
© 2007 Microchip Technology Inc.
Bit 0
BOR
SCS
PS0
VR0
RD
C
(3)
xxxx xxxx
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
---0 0000
0000 000x
--01 q-qq --0u u-uu
-110 q000 -110 x000
---0 0000 ---u uuuu
--00 -000 --00 -000
--00 0000 --00 0000
--11 -111 --11 -111
0-0- 0000 0-0- 0000
---- x000 ---- q000
---- ---- ---- ----
POR/BOR/
Value on
WUR
—
—
—
—
—
—
—
—
—
—
32,137
63,137
32,137
26,137
32,137
32,137
28,137
29,137
Page
—
—
—
—
—
—
—
—
—
—
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