PIC12LF1840-E/P Microchip Technology, PIC12LF1840-E/P Datasheet - Page 19

• Manufacturer Part Number: PIC12LF1840-E/P
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Nano
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 12Fr

Specifications of PIC12LF1840-E/P

• Processor Series: PIC12F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 7 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Core Processor: RISC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 5
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

3.2.2
The Special Function Registers are registers used by
the application to control the desired operation of
peripheral functions in the device. The registers asso-
ciated with the operation of the peripherals are
described in the appropriate peripheral chapter of this
data sheet.
3.2.3
There are up to 80 bytes of GPR in each data memory
bank.
3.2.3.1
The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See
“Linear Data Memory”
3.2.4
There are 16 bytes of common RAM accessible from all
banks.
FIGURE 3-2:
 2011 Microchip Technology Inc.
7-bit Bank Offset
SPECIAL FUNCTION REGISTER
GENERAL PURPOSE RAM
COMMON RAM
Linear Access to GPR
0Ch
0Bh
1Fh
6Fh
7Fh
00h
20h
70h
Special Function Registers
BANKED MEMORY
PARTITIONING
General Purpose RAM
(20 bytes maximum)
(80 bytes maximum)
for more information.
Memory Region
Core Registers
Common RAM
(12 bytes)
(16 bytes)
Section 3.5.2
Preliminary
3.2.5
The memory maps for the device family are as shown
in
TABLE 3-2:
Table
PIC12(L)F1840
3-2.
Device
DEVICE MEMORY MAPS
PIC12(L)F1840
MEMORY MAP TABLES
Banks
24-31
8-23
0-7
31
DS41441B-page 19
Table No.
Table 3-3
Table 3-4
Table 3-5
Table 3-6