PIC16F722-E/MV Microchip Technology, PIC16F722-E/MV Datasheet - Page 200

• Manufacturer Part Number: PIC16F722-E/MV
• Description: 3.5 KB Flash, 1.8V-5.5V, 16 MHz Int. Osc 28 UQFN 4x4x0.5mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F722-E/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-UFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F72X/PIC16LF72X
BTFSS
Syntax:
Operands:
Operation:
Status Affected:
Description:
CALL
Syntax:
Operands:
Operation:
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Description:
CLRF
Syntax:
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Operation:
Status Affected:
Description:
CLRW
Syntax:
Operands:
Operation:
Status Affected:
Description:
DS41341E-page 200
Bit Test f, Skip if Set
[ label ] BTFSS f,b
0 ≤ f ≤ 127
0 ≤ b < 7
skip if (f<b>) = 1
None
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next
instruction is discarded and a NOP
is executed instead, making this a
2-cycle instruction.
Call Subroutine
[ label ] CALL k
0 ≤ k ≤ 2047
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
None
Call Subroutine. First, return
address (PC + 1) is pushed onto
the stack. The eleven-bit
immediate address is loaded into
PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH.
CALL is a two-cycle instruction.
Clear W
[ label ] CLRW
None
00h → (W)
1 → Z
Z
W register is cleared. Zero bit (Z)
is set.
Clear f
[ label ] CLRF
0 ≤ f ≤ 127
00h → (f)
1 → Z
Z
The contents of register ‘f’ are
cleared and the Z bit is set.
f
CLRWDT
Syntax:
Operands:
Operation:
Status Affected:
Description:
COMF
Syntax:
Operands:
Operation:
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Description:
DECF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Complement f
(f) → (destination)
Z
TO, PD
[ label ] COMF
0 ≤ f ≤ 127
d ∈ [0,1]
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’,
the result is stored back in
register ‘f’.
Decrement f
[ label ] DECF f,d
0 ≤ f ≤ 127
d ∈ [0,1]
(f) - 1 → (destination)
Z
Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Clear Watchdog Timer
[ label ] CLRWDT
None
00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
CLRWDT instruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT.
Status bits TO and PD are set.
© 2009 Microchip Technology Inc.
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