PIC16F722-E/MV Microchip Technology, PIC16F722-E/MV Datasheet - Page 238
![3.5 KB Flash, 1.8V-5.5V, 16 MHz Int. Osc 28 UQFN 4x4x0.5mm TUBE](/photos/12/13/121305/c04-152_mv_sml.jpg)
PIC16F722-E/MV
Manufacturer Part Number
PIC16F722-E/MV
Description
3.5 KB Flash, 1.8V-5.5V, 16 MHz Int. Osc 28 UQFN 4x4x0.5mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.AC164112.pdf
(302 pages)
2.PIC16F722-ISS.pdf
(10 pages)
3.PIC16F722-ISS.pdf
(2 pages)
4.PIC16F722-ISS.pdf
(8 pages)
Specifications of PIC16F722-E/MV
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-UFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- AC164112 PDF datasheet
- PIC16F722-ISS PDF datasheet #2
- PIC16F722-ISS PDF datasheet #3
- PIC16F722-ISS PDF datasheet #4
- Current page: 238 of 302
- Download datasheet (5Mb)
PIC16F72X/PIC16LF72X
TABLE 23-13: I
DS41341E-page 238
Note 1:
Param.
SP100* T
SP101* T
SP102* T
SP103* T
SP106* T
SP107* T
SP109* T
SP110* T
SP111
No.
2:
*
These parameters are characterized but not tested.
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A Fast mode (400 kHz) I
the requirement T
not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal,
it must output the next data bit to the SDA line T
the Standard mode I
C
Symbol
SU
AA
R
HIGH
LOW
F
HD
BUF
B
:
:
DAT
DAT
2
C™ BUS DATA REQUIREMENTS
Clock high time
Clock low time
SDA and SCL rise
time
SDA and SCL fall
time
Data input hold time 100 kHz mode
Data input setup
time
Output valid from
clock
Bus free time
Bus capacitive loading
SU
:
2
DAT
C bus specification), before the SCL line is released.
Characteristic
2
≥ 250 ns must then be met. This will automatically be the case if the device does
C
™
bus device can be used in a Standard mode (100 kHz) I
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
R
max. + T
20 + 0.1C
20 + 0.1C
1.5T
1.5T
Min.
250
100
4.0
0.6
4.7
1.3
4.7
1.3
—
—
—
—
—
0
0
CY
CY
SU
B
B
:
DAT
Max.
1000
3500
300
250
250
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
= 1000 + 250 = 1250 ns (according to
Units
μs
μs
μs
μs
μs
μs
μs
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
© 2009 Microchip Technology Inc.
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
C
10-400 pF
C
10-400 pF
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission
can start
B
B
is specified to be from
is specified to be from
2
Conditions
C bus system, but
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