PIC18F25K80-I/MM Microchip Technology, PIC18F25K80-I/MM Datasheet - Page 335
![ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 QFN-S 6x6mm TUBE](/photos/16/12/161267/qfn-28_sml.jpg)
PIC18F25K80-I/MM
Manufacturer Part Number
PIC18F25K80-I/MM
Description
ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 QFN-S 6x6mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F25K80-I/MM
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad
Processor Series
PIC18F25K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3648 B
Interface Type
I2C, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F25K80-I/MM
Manufacturer:
MICROCHIP
Quantity:
2 400
- Current page: 335 of 628
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21.4.17.2
During a Repeated Start condition, a bus collision
occurs if:
a)
b)
When the user deasserts SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD<6:0> and
counts down to 0. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
FIGURE 21-31:
FIGURE 21-32:
2011 Microchip Technology Inc.
A low level is sampled on SDA when SCL goes
from a low level to a high level.
SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘ 1 ’.
SDA
SCL
BCLIF
RSEN
S
SSPIF
SDA
SCL
RSEN
BCLIF
S
SSPIF
Bus Collision During a Repeated
Start Condition
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
Preliminary
T
BRG
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
PIC18F66K80 FAMILY
If SDA is low, a bus collision has occurred (i.e., another
master
Figure
reloaded and begins counting. If SDA goes from
high-to-low before the BRG times out, no bus collision
occurs because no two masters can assert SDA at
exactly the same time.
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘ 1 ’ during the Repeated Start condition
(see
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is complete.
Figure
21-31). If SDA is sampled high, the BRG is
is
21-32).
attempting
Cleared in software
T
BRG
to
Interrupt cleared
in software
transmit
‘0’
‘0’
DS39977C-page 335
‘0’
a
data
‘ 0 ’,
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