PIC18F25K80-I/MM Microchip Technology, PIC18F25K80-I/MM Datasheet - Page 89
![ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 QFN-S 6x6mm TUBE](/photos/16/12/161267/qfn-28_sml.jpg)
PIC18F25K80-I/MM
Manufacturer Part Number
PIC18F25K80-I/MM
Description
ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 QFN-S 6x6mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F25K80-I/MM
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad
Processor Series
PIC18F25K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3648 B
Interface Type
I2C, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F25K80-I/MM
Manufacturer:
MICROCHIP
Quantity:
2 400
- Current page: 89 of 628
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5.7
Most registers are unaffected by a Reset. Their status
is unknown on a Power-on Reset and unchanged by all
other Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
CM, POR and BOR, are set or cleared differently in dif-
TABLE 5-3:
2011 Microchip Technology Inc.
Power-on Reset
RESET Instruction
Brown-out Reset
MCLR Reset during
Power-Managed Run modes
MCLR Reset during
Power-Managed Idle modes and
Sleep mode
WDT Time-out during Full Power
or Power-Managed Run modes
MCLR Reset during Full-Power
execution
Stack Full Reset (STVREN = 1 )
Stack Underflow Reset
(STVREN = 1 )
Stack Underflow Error (not an
actual Reset, STVREN = 0 )
WDT Time-out during
Power-Managed Idle or Sleep
modes
Interrupt Exit from
Power-Managed modes
Legend: u = unchanged
Note 1:
2:
Reset State of Registers
When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
Reset state is ‘ 1 ’ for POR and unchanged for all other Resets when software BOR is enabled
(BOREN<1:0> Configuration bits = 01 and SBOREN = 1 ); otherwise, the Reset state is ‘ 0 ’.
Condition
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Counter
Program
PC + 2
PC + 2
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
(1)
SBOREN CM
u
u
u
u
u
u
u
u
u
u
u
Preliminary
1
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
PIC18F66K80 FAMILY
1
u
1
u
u
u
u
u
u
u
u
u
ferent Reset situations, as indicated in
These bits are used in software to determine the nature
of the Reset.
Table 5-4
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
RCON Register
RI
1
0
1
u
u
u
u
u
u
u
u
u
TO
1
u
1
1
1
0
u
u
u
u
0
u
describes the Reset states for all of the
PD
1
u
1
u
0
u
u
u
u
u
0
0
POR BOR STKFUL STKUNF
0
u
u
u
u
u
u
u
u
u
u
u
0
u
0
u
u
u
u
u
u
u
u
u
STKPTR Register
DS39977C-page 89
0
u
u
u
u
u
u
1
u
u
u
u
Table
0
u
u
u
u
u
u
u
1
1
u
u
5-3.
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