PIC18F25K80-I/MM Microchip Technology, PIC18F25K80-I/MM Datasheet - Page 375
![ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 QFN-S 6x6mm TUBE](/photos/16/12/161267/qfn-28_sml.jpg)
PIC18F25K80-I/MM
Manufacturer Part Number
PIC18F25K80-I/MM
Description
ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 QFN-S 6x6mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F25K80-I/MM
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad
Processor Series
PIC18F25K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3648 B
Interface Type
I2C, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F25K80-I/MM
Manufacturer:
MICROCHIP
Quantity:
2 400
- Current page: 375 of 628
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23.8
A/D conversion can be started by the Special Event
Trigger of any of these modules:
• CCP2 – Requires CCP2M<3:0> bits
• ECCP1
• CTMU – Requires the setting of the CTTRIG bit
• Timer1
To start an A/D conversion:
• The A/D module must be enabled (ADON = 1 )
• The appropriate analog input channel selected
• The minimum acquisition period set one of these
With these conditions met, the trigger sets the
GO/DONE bit and the A/D acquisition starts.
If the A/D module is not enabled (ADON = 0 ), the
module ignores the Special Event Trigger.
2011 Microchip Technology Inc.
(CCP2CON<3:0>) set at ‘ 1011 ’
(CTMUCONH<0>)
ways:
- Timing provided by the user
- Selection made of an appropriate T
Note:
Use of the Special Event Triggers
With an ECCP1 or CCP2 trigger, Timer1
or Timer3 is cleared. The timers reset to
automatically repeat the A/D acquisition
period with minimal software overhead
(moving ADRESH:ADRESL to the desired
location). If the A/D module is not enabled,
the Special Event Trigger is ignored by the
module, but the timer’s counter resets.
(†)
ACQ
time
Preliminary
PIC18F66K80 FAMILY
23.9
The selection of the automatic acquisition time and A/D
conversion clock is determined, in part, by the clock
source and frequency while in a power-managed
mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT<2:0> and
ADCS<2:0> bits in ADCON2 should be updated in
accordance with the power-managed mode clock that
will be used.
After the power-managed mode is entered (either of the
power-managed Run modes), an A/D acquisition or
conversion may be started. Once an acquisition or con-
version is started, the device should continue to be
clocked by the same power-managed mode clock source
until the conversion has been completed. If desired, the
device
power-managed Idle mode during the conversion.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in Sleep mode requires that the A/D RC
clock be selected. If bits, ACQT<2:0>, are set to ‘ 000 ’
and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEP instruction and entry into Sleep mode. The
IDLEN and SCS<1:0> bits in the OSCCON register
must have already been cleared prior to starting the
conversion.
may
Operation in Power-Managed
Modes
be
placed
into the
DS39977C-page 375
corresponding
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