PIC18F26K80-I/MM Microchip Technology, PIC18F26K80-I/MM Datasheet - Page 225
![ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 QFN-S 6x6mm TUBE](/photos/16/12/161267/qfn-28_sml.jpg)
PIC18F26K80-I/MM
Manufacturer Part Number
PIC18F26K80-I/MM
Description
ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 QFN-S 6x6mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F26K80-I/MM
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad
Processor Series
PIC18F26K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3648 B
Interface Type
I2C, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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14.8.4
When Timer1 Gate Single Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer1
Gate Single Pulse mode is enabled by setting the
T1GSPM bit (T1GCON<4>) and the T1GGO/T1DONE
bit (T1GCON<3>). The Timer1 will be fully enabled on
the next incrementing edge.
On the next trailing edge of the pulse, the T1GGO/
T1DONE bit will automatically be cleared. No other
gate events will be allowed to increment Timer1 until
the T1GGO/T1DONE bit is once again set in software.
FIGURE 14-6:
2011 Microchip Technology Inc.
TMR1GE
T1GSPM
T1DONE
T1GPOL
T1GVAL
T1GGO/
T1G_IN
Timer1
T1CKI
TIMER1 GATE SINGLE PULSE
MODE
TIMER1 GATE SINGLE PULSE MODE
N
Counting Enabled on
Rising Edge of T1G
Set by Software
Preliminary
N + 1
PIC18F66K80 FAMILY
Clearing the T1GSPM bit of the T1GCON register will
also clear the T1GGO/T1DONE bit. (For timing details,
see
Simultaneously enabling the Toggle and Single Pulse
modes will permit both sections to work together. This
allows the cycle times on the Timer1 gate source to be
measured. (For timing details, see
14.8.5
When the Timer1 gate value status is utilized, it is
possible to read the most current level of the gate
control value. The value is stored in the T1GVAL bit
(T1GCON<2>). This bit is valid even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
Figure
Cleared by Hardware on
Falling Edge of T1GVAL
14-6.)
TIMER1 GATE VALUE STATUS
N + 2
Figure
DS39977C-page 225
14-7.)
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