PIC18F43K20-I/ML Microchip Technology, PIC18F43K20-I/ML Datasheet - Page 270
![8 KB Enh Flash, 768 RAM, 36 I/O, Nanowatt XLP 44 QFN 8x8x0.9mm TUBE](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F43K20-I/ML
Manufacturer Part Number
PIC18F43K20-I/ML
Description
8 KB Enh Flash, 768 RAM, 36 I/O, Nanowatt XLP 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(456 pages)
3.PIC18F23K20-ISS.pdf
(10 pages)
Specifications of PIC18F43K20-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F2XK20/4XK20
19.2.9
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
1.
2.
3.
4.
5.
6.
7.
8.
DS41303G-page 270
Note 1: The global interrupt can be disabled if the
Configure Port:
• Disable pin output driver (See TRIS register)
• Configure pin as analog
Configure the ADC module:
• Select ADC conversion clock
• Configure voltage reference
• Select ADC input channel
• Select result format
• Select acquisition delay
• Turn on ADC module
Configure ADC interrupt (optional):
• Clear ADC interrupt flag
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt
Wait the required acquisition time
Start conversion by setting the GO/DONE bit.
Wait for ADC conversion to complete by one of
the following:
• Polling the GO/DONE bit
• Waiting for the ADC interrupt (interrupts
Read ADC Result
Clear the ADC interrupt flag (required if interrupt
is enabled).
enabled)
2: Software delay required if ACQT bits are
A/D CONVERSION PROCEDURE
user is attempting to wake-up from Sleep
and resume in-line code execution.
set to zero delay. See Section 19.3 “A/D
Acquisition Requirements”.
(1)
(2)
.
EXAMPLE 19-1:
;This code block configures the ADC
;for polling, Vdd and Vss as reference, Frc
clock and AN0 input.
;
;Conversion start & polling for completion
; are included.
;
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
MOVLW
MOVWF
BSF
ADCPoll:
BTFSC
BRA
; Result is complete - store 2 MSbits in
; RESULTHI and 8 LSbits in RESULTLO
MOVFF
MOVFF
B’10101111’ ;right justify, Frc,
ADCON2
B’00000000’ ;ADC ref = Vdd,Vss
ADCON1
TRISA,0
ANSEL,0
B’00000001’ ;AN0, ADC on
ADCON0
ADCON0,GO
ADCON0,GO
ADCPoll
ADRESH,RESULTHI
ADRESL,RESULTLO
A/D CONVERSION
2010 Microchip Technology Inc.
; & 12 TAD ACQ time
;
;Set RA0 to input
;Set RA0 to analog
;
;Start conversion
;Is conversion done?
;No, test again
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