PIC18F43K20-I/ML Microchip Technology, PIC18F43K20-I/ML Datasheet - Page 49
![8 KB Enh Flash, 768 RAM, 36 I/O, Nanowatt XLP 44 QFN 8x8x0.9mm TUBE](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F43K20-I/ML
Manufacturer Part Number
PIC18F43K20-I/ML
Description
8 KB Enh Flash, 768 RAM, 36 I/O, Nanowatt XLP 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(456 pages)
3.PIC18F23K20-ISS.pdf
(10 pages)
Specifications of PIC18F43K20-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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3.5.4
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
• the primary clock source is not any of the LP, XT,
TABLE 3-3:
2010 Microchip Technology Inc.
Note 1:
is not stopped and
HS or HSPLL modes.
T1OSC or LFINTOSC
Primary Device Clock
2:
3:
4:
(PRI_IDLE mode)
before Wake-up
Clock Source
HFINTOSC
(Sleep mode)
T
with any other required delays (see Section 3.4 “Idle Modes”). On Reset, HFINTOSC defaults to 1 MHz.
Includes both the HFINTOSC 16 MHz source and postscaler derived frequencies.
T
Execution continues during the HFINTOSC stabilization period, T
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
CSD
OST
None
is the Oscillator Start-up Timer (parameter 32). t
(parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
(2)
(1)
after Wake-up
Clock Source
HFINTOSC
HFINTOSC
HFINTOSC
HFINTOSC
LP, XT, HS
LP, XT, HS
LP, XT, HS
LP, XT, HS
EC, RC
EC, RC
EC, RC
EC, RC
HSPLL
HSPLL
HSPLL
HSPLL
(2)
(1)
(1)
(1)
In these instances, the primary clock source either
does not require an oscillator start-up delay since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC, INTOSC,
and INTOSCIO modes). However, a fixed delay of
interval T
when leaving Sleep and Idle modes to allow the CPU
to prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
PIC18F2XK20/4XK20
PLL
is the PLL Lock-out Timer (parameter F12).
CSD
T
T
T
OST
OST
OST
Exit Delay
T
T
T
T
T
T
T
T
T
IOBST
IOBST
IOBST
following the wake event is still required
None
CSD (1)
OST
CSD
OST
CSD
OST
CSD
+ t
+ t
+ t
(3)
PLL
(1)
(4)
PLL
(1)
(3)
PLL
(1)
(4)
(4)
(parameter 39).
(3)
(3)
(3)
Clock Ready Status
Bit (OSCCON)
DS41303G-page 49
OSTS
OSTS
OSTS
OSTS
IOFS
IOFS
IOFS
IOFS
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