PIC18F43K20-I/ML Microchip Technology, PIC18F43K20-I/ML Datasheet - Page 271
![8 KB Enh Flash, 768 RAM, 36 I/O, Nanowatt XLP 44 QFN 8x8x0.9mm TUBE](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F43K20-I/ML
Manufacturer Part Number
PIC18F43K20-I/ML
Description
8 KB Enh Flash, 768 RAM, 36 I/O, Nanowatt XLP 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(456 pages)
3.PIC18F23K20-ISS.pdf
(10 pages)
Specifications of PIC18F43K20-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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19.2.10
The following registers are used to control the opera-
tion of the ADC.
REGISTER 19-1:
2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-2
bit 1
bit 0
Note 1:
Note:
U-0
—
2:
These channels are not implemented on PIC18F2XK20 devices.
Allow greater than 15 s acquisition time when measuring the Fixed Voltage Reference.
ADC REGISTER DEFINITIONS
Analog pin control is performed by the
ANSEL and ANSELH registers. For ANSEL
and ANSELH registers, see Register 10-2
and Register 10-3, respectively.
Unimplemented: Read as ‘0’
CHS<3:0>: Analog Channel Select bits
0000 = AN0
0001 = AN1
0010 = AN2
0011 = AN3
0100 = AN4
0101 = AN5
0110 = AN6
0111 = AN7
1000 = AN8
1001 = AN9
1010 = AN10
1011 = AN11
1100 = AN12
1101 = Reserved
1110 = Reserved
1111 = FVR (1.2 Volt Fixed Voltage Reference)
GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
0 = A/D conversion completed/not in progress
ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
This bit is automatically cleared by hardware when the A/D conversion has completed.
U-0
—
ADCON0: A/D CONTROL REGISTER 0
(1)
(1)
(1)
W = Writable bit
‘1’ = Bit is set
CHS3
R/W-0
CHS2
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CHS1
R/W-0
PIC18F2XK20/4XK20
(2)
CHS0
R/W-0
x = Bit is unknown
GO/DONE
R/W-0
DS41303G-page 271
ADON
R/W-0
bit 0
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