PIC18F87J50T-I/PT Microchip Technology, PIC18F87J50T-I/PT Datasheet - Page 159

• Manufacturer Part Number: PIC18F87J50T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J50T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 65
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F87J50T-I/PTTR

TABLE 10-16: PORTG FUNCTIONS
© 2009 Microchip Technology Inc.
RG0/PMA8/
ECCP3/P3A
RG1/PMA7/
TX2/CK2/
RG2/PMA6/
RX2/DT2
RG3/PMCS1/
CCP4/P3D
RG4/PMCS2/
CCP5/P1D
Legend:
Pin Name
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Function
ECCP3
PMCS1
PMCS2
PMA8
PMA7
PMA6
CCP4
CCP5
RG0
RG1
RG2
RG3
RG4
P3A
TX2
CK2
RX2
DT2
P3D
P1D
Setting
TRIS
0
1
x
0
0
1
x
1
1
1
0
1
x
1
1
1
0
1
x
x
0
1
0
0
1
x
0
1
0
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
Type
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
TTL
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ECCP3 Enhanced PWM output, channel A; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Parallel Master Port address.
Synchronous serial data output (EUSART2 module); takes priority over
port data.
Synchronous serial data input (EUSART2 module). User must configure
as an input.
LATG<2> data output.
Parallel Master Port address.
Asynchronous serial receive data input (EUSART2 module).
Synchronous serial data output (EUSART2 module); takes priority over
port data.
Synchronous serial data input (EUSART2 module). User must configure
as an input.
LATG<3> data output.
PORTG<3> data input.
Parallel Master Port address chip select 1
Parallel Master Port address chip select 1 in.
CCP4 compare output and CCP4 PWM output; takes priority over port data.
CCP4 capture input.
ECCP3 Enhanced PWM output, channel D; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATG<4> data output.
PORTG<4> data input.
Parallel Master Port address chip select 2
CCP5 compare output and CCP5 PWM output; takes priority over port data.
CCP5 capture input.
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATG<0> data output.
PORTG<0> data input.
Parallel Master Port address.
ECCP3 compare and PWM output; takes priority over port data.
ECCP3 capture input.
LATG<1> data output.
PORTG<1> data input.
Synchronous serial clock input (EUSART2 module).
PORTG<2> data input.
ECCP1 Enhanced PWM output, channel D; takes priority over port and
PIC18F87J50 FAMILY
Description
DS39775C-page 159