PIC18F87J50T-I/PT Microchip Technology, PIC18F87J50T-I/PT Datasheet - Page 82

• Manufacturer Part Number: PIC18F87J50T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J50T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 65
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F87J50T-I/PTTR

PIC18F87J50 FAMILY
5.3.5.1
In several locations in the SFR bank, a single address
is used to access two different hardware registers. In
these cases, a “legacy” register of the standard PIC18
SFR set (such as OSCCON, T1CON, etc.) shares its
address with an alternate register. These alternate reg-
isters are associated with enhanced configuration
options for peripherals, or with new device features not
included in the standard PIC18 SFR map. A complete
list of shared register addresses and the registers
associated with them is provided in Table 5-4.
Access to the alternate registers is enabled in software
by setting the ADSHR bit in the WDTCON register
(Register 5-3). ADSHR must be manually set or
cleared to access the alternate or legacy registers, as
required. Since the bit remains in a given state until
changed, users should always verify the state of
ADSHR before writing to any of the shared SFR
addresses.
TABLE 5-4:
REGISTER 5-3:
DS39775C-page 82
Legend:
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-1
bit 0
FCFh
FCEh
FD3h
REGSLP
Address
R/W-0
(D)
(D)
(D)
(A)
(A)
(A)
(D) = Default SFR, accessible only when ADSHR = 0; (A) = Alternate SFR, accessible only when ADSHR = 1.
Implemented in 80-pin devices only.
Shared Address SFRs
REGSLP: Voltage Regulator Low-Power Operation Enable bit
For details of bit operation, see Register 25-9 on page 359.
LVDSTAT: Low-Voltage Detect Status bit
1 = V
0 = V
Unimplemented: Read as ‘0’
ADSHR: Shared Address SFR Select bit
1 = Alternate SFR is selected
0 = Default (legacy) SFR is selected
Unimplemented: Read as ‘0’
SWDTEN: Software Controlled Watchdog Timer Enable bit
For details of bit operation, see Register 25-9.
LVDSTAT
SHARED SFR ADDRESSES FOR PIC18F87J50 FAMILY DEVICES
REFOCON
R-x
OSCCON
ODCON1
ODCON2
DDCORE
DDCORE
TMR1H
TMR1L
Name
WDTCON: WATCHDOG TIMER CONTROL REGISTER
> 2.45V nominal
< 2.45V nominal
W = Writable bit
‘1’ = Bit is set
U-0
—
FCDh
FCCh
FCBh
Address
ADSHR
R/W-0
(D)
(A)
(D)
(A)
(D)
(A)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
MEMCON
PADCFG1
ODCON3
5.3.5.2
In addition to the shared address SFRs, there are sev-
eral registers that share the same address in the SFR
space, but are not accessed with the ADSHR bit.
Instead, the register’s definition and use depends on
the operating mode of its associated peripheral. These
registers are:
• SSPxADD and SSPxMSK: These are two sepa-
• PMADDRH/L and PMDOUT2H/L: In this case,
T1CON
Name
TMR2
U-0
PR2
—
rate hardware registers, accessed through a
single SFR address. The operating mode of the
MSSP modules determines which register is
being accessed. See Section 19.4.3.4 “7-Bit
Address Masking Mode” for additional details.
these named buffer pairs are actually the same
physical registers. The PMP module’s operating
mode determines what function the registers take
on. See Section 11.1.2 “Data Registers” for
additional details.
(1)
Context Defined SFRs
U-0
—
FC2h
FC1h
F77h
© 2009 Microchip Technology Inc.
Address
x = Bit is unknown
U-0
—
(D)
(A)
(D)
(A)
(D)
(A)
CVRCON
ADCON0
ANCON1
ADCON1
ANCON0
SWDTEN
Name
PR4
U-0
bit 0