PIC18LF14K22-E/ML Microchip Technology, PIC18LF14K22-E/ML Datasheet - Page 39
![16KB Flash, 512bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 QFN 4x4mm TUB](/photos/16/12/161232/qfn-20-bottom_sml.jpg)
PIC18LF14K22-E/ML
Manufacturer Part Number
PIC18LF14K22-E/ML
Description
16KB Flash, 512bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 QFN 4x4mm TUB
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18LF13K22-ISS.pdf
(388 pages)
Specifications of PIC18LF14K22-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
A/d Bit Size
10 bit
A/d Channels Available
12
Height
0.88 mm
Length
4 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.8 V, 2.7 V
Width
4 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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TABLE 3-2:
2010 Microchip Technology Inc.
TOSU
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
PREINC0
PLUSW0
FSR0H
FSR0L
WREG
INDF1
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
PREINC1
PLUSW1
FSR1H
FSR1L
BSR
INDF2
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
PREINC2
PLUSW2
FSR2H
FSR2L
STATUS
Legend:
Note
File Name
1:
2:
Top-of-Stack, High Byte (TOS<15:8>)
Top-of-Stack, Low Byte (TOS<7:0>)
Holding Register for PC<15:8>
PC, Low Byte (PC<7:0>)
Program Memory Table Pointer, High Byte (TBLPTR<15:8>)
Program Memory Table Pointer, Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register, High Byte
Product Register, Low Byte
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – value
of FSR0 offset by W
Indirect Data Memory Address Pointer 0, Low Byte
Working Register
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – value
of FSR1 offset by W
Indirect Data Memory Address Pointer 1, Low Byte
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – value
of FSR2 offset by W
Indirect Data Memory Address Pointer 2, Low Byte
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 21.4 “Brown-out Reset (BOR)”.
The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is
read-only.
GIE/GIEH
STKOVF
RABPU
INT2IP
Bit 7
—
—
—
—
—
—
—
—
REGISTER FILE SUMMARY (PIC18F1XK22/LF1XK22)
PEIE/GIEL
INTEDG0
STKUNF
INT1IP
Bit 6
—
—
—
—
—
—
—
—
INTEDG1
TMR0IE
Bit 5
—
—
—
—
—
—
—
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
Holding Register for PC<20:16>
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
INTEDG2
INT2IE
INT0IE
Bit 4
SP4
—
—
—
—
N
Preliminary
Indirect Data Memory Address Pointer 0, High Byte
Indirect Data Memory Address Pointer 1, High Byte
Bank Select Register
Indirect Data Memory Address Pointer 2, High Byte
PIC18F1XK22/LF1XK22
INT1IE
RABIE
Bit 3
SP3
OV
—
TMR0IF
TMR0IP
Bit 2
SP2
—
Z
INT0IF
INT2IF
Bit 1
SP1
DC
—
RABIP
INT1IF
RABIF
Bit 0
SP0
C
DS41365D-page 39
---0 0000 257, 28
0000 0000 257, 28
0000 0000 257, 28
00-0 0000 257, 29
---0 0000 257, 28
0000 0000 257, 28
0000 0000 257, 28
---0 0000 257, 52
0000 0000 257, 52
0000 0000 257, 52
0000 0000 257, 52
xxxx xxxx 257, 63
xxxx xxxx 257, 63
0000 000x 257, 67
1111 -1-1 257, 68
11-0 0-00 257, 69
---- 0000 257, 44
xxxx xxxx 257, 44
xxxx xxxx
---- 0000 258, 44
xxxx xxxx 258, 44
---- 0000 258, 33
---- 0000 258, 44
xxxx xxxx 258, 44
---x xxxx 258, 42
POR, BOR
Value on
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Details
257, 44
257, 44
257, 44
257, 44
257, 44
257, 44
257, 44
257, 44
257, 44
257, 44
258, 44
258, 44
258, 44
258, 44
258, 44
page:
257
on
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