PIC18LF14K22-E/SO Microchip Technology, PIC18LF14K22-E/SO Datasheet - Page 272
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PIC18LF14K22-E/SO
Manufacturer Part Number
PIC18LF14K22-E/SO
Description
16KB Flash, 512bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 SOIC .300in T
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18LF13K22-ISS.pdf
(388 pages)
Specifications of PIC18LF14K22-E/SO
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F1XK22/LF1XK22
22.2.1
Register 22-14 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT enable
Configuration bit, but only if the Configuration bit has
disabled the WDT.
REGISTER 22-14: WDTCON: WATCHDOG TIMER CONTROL REGISTER
TABLE 22-2:
22.3
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC
The user program memory is divided into five blocks.
One of these is a boot block of 0.5K or 2K bytes,
depending on the device. The remainder of the mem-
ory is divided into individual blocks on binary boundar-
ies.
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
DS41365D-page 272
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-1
bit 0
CONFIG2H
RCON
WDTCON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.
®
Name
microcontroller devices.
U-0
—
Program Verification and
Code Protection
CONTROL REGISTER
Unimplemented: Read as ‘0’
SWDTEN: Software Enable or Disable the Watchdog Timer bit
1 = WDT is turned on
0 = WDT is turned off (Reset value)
IPEN
Bit 7
SUMMARY OF WATCHDOG TIMER REGISTERS
—
—
U-0
—
SBOREN
Bit 6
—
—
W = Writable bit
‘1’ = Bit is set
U-0
—
Bit 5
—
—
—
WDTPS3 WDTPS2 WDTPS1 WDTPS0
U-0
Preliminary
—
Bit 4
RI
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Bit 3
Figure 22-2 shows the program memory organization
for 8, 16 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 22-3.
U-0
TO
—
—
Bit 2
PD
—
U-0
(1)
—
Bit 1
POR
2010 Microchip Technology Inc.
—
x = Bit is unknown
U-0
—
SWDTEN
WDTEN
Bit 0
BOR
SWDTEN
R/W-0
on page
Values
Reset
265
258
258
bit 0
(1)
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