PIC18LF14K22-E/SO Microchip Technology, PIC18LF14K22-E/SO Datasheet - Page 55
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PIC18LF14K22-E/SO
Manufacturer Part Number
PIC18LF14K22-E/SO
Description
16KB Flash, 512bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 SOIC .300in T
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18LF13K22-ISS.pdf
(388 pages)
Specifications of PIC18LF14K22-E/SO
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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4.4
The minimum erase block is 32 words or 64 bytes. Only
through the use of an external programmer, or through
ICSP™ control, can larger blocks of program memory
be bulk erased. Word erase in the Flash array is not
supported.
When initiating an erase sequence from the Microcon-
troller itself, a block of 64 bytes of program memory is
erased. The Most Significant
TBLPTR<21:6> point to the block being erased. The
TBLPTR<5:0> bits are ignored.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the Flash pro-
gram memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.
The write initiate sequence for EECON2, shown as
steps 4 through 6 in Section 4.4.1 “Flash Program
Memory Erase Sequence”, is used to guard against
accidental writes. This is sometimes referred to as a
long write.
A long write is necessary for erasing the internal
Flash. Instruction execution is halted during the long
write cycle. The long write is terminated by the internal
programming timer.
EXAMPLE 4-2:
2010 Microchip Technology Inc.
Required
Sequence
Erasing Flash Program Memory
ERASE_BLOCK
ERASING A FLASH PROGRAM MEMORY BLOCK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BCF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
16 bits of the
Preliminary
PIC18F1XK22/LF1XK22
4.4.1
The sequence of events for erasing a block of internal
program memory is:
1.
2.
3.
4.
5.
6.
7.
8.
; load TBLPTR with the base
; address of the memory block
; point to Flash program memory
; access Flash program memory
; enable write to memory
; enable block Erase operation
; disable interrupts
; write 55h
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
Load Table Pointer register with address of
block being erased.
Set the EECON1 register for the erase operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN bit to enable writes;
• set FREE bit to enable the erase.
Disable interrupts.
Write 55h to EECON2.
Write 0AAh to EECON2.
Set the WR bit. This will begin the block erase
cycle.
The CPU will stall for duration of the erase
(about 2 ms using internal timer).
Re-enable interrupts.
FLASH PROGRAM MEMORY
ERASE SEQUENCE
DS41365D-page 55
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