PIC24FJ128GA308-I/PT Microchip Technology, PIC24FJ128GA308-I/PT Datasheet - Page 81

• Manufacturer Part Number: PIC24FJ128GA308-I/PT
• Description: 16-bit, 16 MIPS, 128 KB Flash, 8 KB RAM, 69 I/O, LCD, XLP W/Vbat 80 TQFP 12x12x1
• Manufacturer: Microchip Technology

REGISTER 5-3:
 2010-2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-1
bit 0
Note 1:
DBUFWF
HIGHIF
R/W-0
R-0
2:
(1,2)
(1)
Setting these flags in software does not generate an interrupt.
Testing for address limit violations (DMASRC or DMADST is either greater than DMAH or less than
DMAL) is NOT done before the actual access.
DBUFWF: Buffered Data Write Flag bit
1 = The content of the DMA buffer has not been written to the location specified in DMADST, or
0 = The content of the DMA buffer has been written to the location specified in DMADST, or DMASRC
Unimplemented: Read as ‘0’
CHSEL<5:0>: DMA Channel Trigger Selection bits
See
HIGHIF: DMA High Address Limit Interrupt Flag bit
1 = The DMA channel has attempted to access an address higher than DMAH, or the upper limit of the
0 = The DMA channel has not invoked the high address limit interrupt.
LOWIF: DMA Low Address Limit Interrupt Flag bit
1 = The DMA channel has attempted to access the DMA SFR address lower than DMAL, but above
0 = The DMA channel has not invoked the low address limit interrupt
DONEIF: DMA Complete Operation Interrupt Flag bit
If CHEN = 1:
1 = The previous DMA session has ended with completion
0 = The current DMA session has not yet completed
If CHEN = 0:
1 = The previous DMA session has ended with completion
0 = The previous DMA session has ended without completion
HALFIF: DMA 50% Water Mark Level Interrupt Flag bit
1 = DMACNT has reached the halfway point to 0000h
0 = DMACNT has not reached the halfway point
OVRUNIF: DMA Channel Overrun Flag bit
1 = The DMA channel is triggered while it is still completing the operation based on the previous trigger
0 = The overrun condition has not occurred
Unimplemented: Read as ‘0’
HALFEN: Halfway Completion Water Mark bit
1 = Interrupts are invoked when DMACNT has reached its halfway point and at completion
0 = An interrupt is invoked only at the completion of the transfer
LOWIF
R/W-0
DMASRC in Null Write mode
in Null Write mode
data RAM space.
the SFR range (07FFh)
Table 5-1
U-0
—
DMAINTn: DMA CHANNEL n INTERRUPT REGISTER
(1,2)
for a complete list.
W = Writable bit
‘1’ = Bit is set
DONEIF
CHSEL5
R/W-0
R/W-0
(1)
HALFIF
PIC24FJ128GA310 FAMILY
CHSEL4
R/W-0
R/W-0
(1)
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
OVRUNIF
CHSEL3
R/W-0
R/W-0
(1,2)
(1,2)
(1)
(1)
(1)
CHSEL2
R/W-0
U-0
—
x = Bit is unknown
CHSEL1
R/W-0
U-0
—
DS39996F-page 81
HALFEN
CHSEL0
R/W-0
R/W-0
bit 8
bit 0