PIC24FJ128GA308-I/PT Microchip Technology, PIC24FJ128GA308-I/PT Datasheet - Page 99

• Manufacturer Part Number: PIC24FJ128GA308-I/PT
• Description: 16-bit, 16 MIPS, 128 KB Flash, 8 KB RAM, 69 I/O, LCD, XLP W/Vbat 80 TQFP 12x12x1
• Manufacturer: Microchip Technology

The CORCON register contains the IPL3 bit, which
together with the IPL<2:0> bits, indicate the current
CPU priority level. IPL3 is a read-only bit so that trap
events cannot be masked by the user software.
The interrupt controller has the Interrupt Controller Test
register, INTTREG, which displays the status of the
interrupt controller. When an interrupt request occurs,
it’s associated vector number and the new interrupt
REGISTER 8-1:
 2010-2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-9
bit 7-5
Note 1:
IPL2
R/W-0
U-0
—
2:
3:
(2,3)
See
interrupt control functions.
The IPL bits are concatenated with the IPL3 (CORCON<3>) bit to form the CPU interrupt priority level.
The value in parentheses indicates the interrupt priority level if IPL3 = 1.
The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
Register 3-1
Unimplemented: Read as ‘0’
IPL<2:0>: CPU Interrupt Priority Level Status bits
111 = CPU interrupt priority level is 7 (15); user interrupts are disabled
110 = CPU interrupt priority level is 6 (14)
101 = CPU interrupt priority level is 5 (13)
100 = CPU interrupt priority level is 4 (12)
011 = CPU interrupt priority level is 3 (11)
010 = CPU interrupt priority level is 2 (10)
001 = CPU interrupt priority level is 1 (9)
000 = CPU interrupt priority level is 0 (8)
IPL1
R/W-0
U-0
—
SR: ALU STATUS REGISTER (IN CPU)
(2,3)
for the description of the remaining bits (bits 8, 4, 3, 2, 1 and 0) that are not dedicated to
HSC = Hardware Settable/Clearable bit
W = Writable bit
‘1’ = Bit is set
IPL0
R/W-0
U-0
—
(2,3)
PIC24FJ128GA310 FAMILY
RA
U-0
R-0
—
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
priority level are latched into INTTREG. This informa-
tion can be used to determine a specific interrupt
source if a generic ISR is used for multiple vectors
(such as when ISR remapping is used in bootloader
applications) or to check if another interrupt is pending
while in an ISR.
All interrupt registers are described in
through
U-0
N
—
(1)
(2,3)
Register 8-44
R/W-0
OV
U-0
—
(1)
in the succeeding pages.
x = Bit is unknown
R/W-0
U-0
Z
—
(1)
DS39996F-page 99
Register 8-1
R/W-0
DC
C
R-0
(1)
(1)
bit 8
bit 0