PIC24FJ32GA104-I/PT Microchip Technology, PIC24FJ32GA104-I/PT Datasheet - Page 225

• Manufacturer Part Number: PIC24FJ32GA104-I/PT
• Description: 16-bit, 16 MIPS, 32KB Flash, 8KB RAM, Nanowatt XLP 44 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ32GA104-I/PT

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (11K x 24)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER 21-5:
 2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-0
Note 1:
PCFG15
R/W-0
PCFG7
R/W-0
(1)
Analog channels, AN6, AN7, AN8 and AN12, are unavailable on 28-pin devices; leave these corresponding
bits set.
PCFG15: A/D Input Band Gap Reference Enable bit
1 = Internal band gap (V
0 = Internal band gap reference channel is enabled
PCFG14: A/D Input Half Band Gap Reference Enable bit
1 = Internal half band gap (V
0 = Internal half band gap reference channel is enabled
PCFG13: A/D Input Voltage Regulator Output Reference Enable bit
1 = Internal voltage regulator output (V
0 = Internal voltage regulator output reference channel is enabled
PCFG<12:0>: Analog Input Pin Configuration Control bits
1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read is enabled
0 = Pin is configured in Analog mode; I/O port read is disabled, A/D samples pin voltage
PCFG14
R/W-0
PCFG6
R/W-0
AD1PCFG: A/D PORT CONFIGURATION REGISTER
(1)
W = Writable bit
‘1’ = Bit is set
PCFG13
PCFG5
R/W-0
R/W-0
BG
) reference channel is disabled
BG
R/W-0
PCFG12
/2) reference channel is disabled
PCFG4
R/W-0
PIC24FJ64GA104 FAMILY
(1)
DDCORE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PCFG11
PCFG3
) reference channel is disabled
R/W-0
R/W-0
(1)
PCFG10
PCFG2
R/W-0
R/W-0
x = Bit is unknown
PCFG9
PCFG1
R/W-0
R/W-0
DS39951C-page 225
R/W-0
PCFG0
PCFG8
R/W-0
(1)
bit 8
bit 0