PIC24FJ32GA104-I/PT Microchip Technology, PIC24FJ32GA104-I/PT Datasheet - Page 46

• Manufacturer Part Number: PIC24FJ32GA104-I/PT
• Description: 16-bit, 16 MIPS, 32KB Flash, 8KB RAM, Nanowatt XLP 44 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ32GA104-I/PT

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (11K x 24)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 4-23:
TABLE 4-24:
TABLE 4-25:
TABLE 4-26:
DSCON
DSWAKE
DSGPR0
DSGPR1
Legend:
Note 1:
RCON
OSCCON
CLKDIV
OSCTUN
REFOCON
Legend:
Note 1:
NVMCON
NVMKEY
Legend:
Note 1:
PMD1
PMD2
PMD3
PMD4
Legend:
File Name
File Name
File Name
File Name
2:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
The Deep Sleep registers are only reset on a V
Addr
0760
0766
Addr
075A
075C
075E
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
The Reset value of the RCON register is dependent on the type of Reset event. See Section 6.0 “Resets” for more information.
The Reset value of the OSCCON register is dependent on both the type of Reset event and the device configuration. See Section 8.0 “Oscillator Configuration” for more information.
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
0740
074E
758
0742
0744
0748
Addr
0770
0772
0774
0776
SYSTEM REGISTER MAP
DEEP SLEEP REGISTER MAP
NVM REGISTER MAP
PMD REGISTER MAP
DSEN
Bit 15
Bit 15
TRAPR
ROEN
Bit 15
T5MD
Bit 15
WR
—
—
ROI
—
—
—
—
—
IOPUWR
Bit 14
WREN
COSC2
Bit 14
DOZE2
Bit 14
Bit 14
T4MD
—
—
—
—
—
—
—
—
WRERR
ROSSLP
Bit 13
Bit 13
COSC1
DOZE1
Bit 13
T3MD
Bit 13
—
—
—
—
—
—
—
—
Bit 12
COSC0
DOZE0
ROSEL
Bit 12
IC5MD
Bit 12
T2MD
Bit 12
—
—
—
—
—
—
—
—
DD
POR event.
Bit 11
RODIV3
DOZEN
IC4MD
Bit 11
Bit 11
T1MD
Bit 11
—
—
—
—
—
—
—
—
—
CMPMD RTCCMD PMPMD
Bit 10
RCDIV2
RODIV2
NOSC2
IC3MD
DPSLP
Bit 10
Bit 10
Bit 10
—
—
—
—
—
—
—
RCDIV1
RODIV1
Deep Sleep General Purpose Register 0
Deep Sleep General Purpose Register 1
IC2MD
NOSC1
Bit 9
Bit 9
Bit 9
Bit 9
—
—
CM
—
—
—
—
—
DSINT0
RCDIV0
RODIV0
PMSLP
NOSC0
Bit 8
IC1MD
Bit 8
Bit 8
—
Bit 8
—
—
—
—
—
I2C1MD
CRCMD
CLKLOCK
DSFLT
Bit 7
Bit 7
Bit 7
EXTR
Bit 7
—
—
—
—
—
—
—
ERASE
U2MD
IOLOCK
Bit 6
Bit 6
Bit 6
SWR
—
—
—
Bit 6
—
—
—
—
—
SWDTEN
U1MD
Bit 5
Bit 5
Bit 5
LOCK
TUN5
Bit 5
—
—
—
—
—
—
—
—
NVMKEY Register<7:0>
DSWDT
SPI2MD
OC5MD
Bit 4
Bit 4
Bit 4
WDTO
TUN4
—
Bit 4
—
—
—
—
—
—
NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000
REFOMD CTMUMD
SPI1MD
DSRTC
OC4MD
Bit 3
SLEEP
Bit 3
Bit 3
TUN3
Bit 3
—
—
CF
—
—
DSMCLR
OC3MD
POSCEN SOSCEN OSWEN
Bit 2
Bit 2
Bit 2
TUN2
Bit 2
IDLE
—
—
—
—
—
DSBOR RELEASE
OC2MD
I2C2MD
LVDMD
Bit 1
Bit 1
Bit 1
TUN1
—
Bit 1
BOR
—
—
—
ADC1MD
DSPOR
OC1MD
Bit 0
Bit 0
Bit 0
TUN0
Bit 0
POR
—
—
—
—
Resets
Resets
Resets
0000
Resets
0000
0001
0000
0000
0000
0000
0000
0000
Note 1
Note 2
0100
0000
0000
All
All
All
All
(1)
(1)