PIC24HJ128GP506A-I/MR Microchip Technology, PIC24HJ128GP506A-I/MR Datasheet - Page 71
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PIC24HJ128GP506A-I/MR
Manufacturer Part Number
PIC24HJ128GP506A-I/MR
Description
16 Bit MCU 40MIPS 128KB FLASH 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ64GP206A-IMR.pdf
(304 pages)
3.PIC24HJ64GP206A-IMR.pdf
(10 pages)
Specifications of PIC24HJ128GP506A-I/MR
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (43K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 18x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8192 B
Interface Type
SPI, I2C, UART
Maximum Clock Frequency
7.37 MHz
Number Of Timers
13
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 140 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- PIC24HJ12GP201-ISO PDF datasheet
- PIC24HJ64GP206A-IMR PDF datasheet #2
- PIC24HJ64GP206A-IMR PDF datasheet #3
- Current page: 71 of 304
- Download datasheet (3Mb)
TABLE 6-3:
6.2.1
The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially
low-frequency crystals) have a relatively long start-up
time. Therefore, one or more of the following conditions
is possible after the Reset signal is released:
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has not expired (if a
• The PLL has not achieved a lock (if PLL is used).
The device will not begin to execute code until a valid
clock source has been released to the system. There-
fore, the oscillator and PLL start-up delays must be
considered when the Reset delay time must be known.
6.2.2
If the FSCM is enabled, it begins to monitor the system
clock source when the Reset signal is released. If a
valid clock source is not available at this time, the
device automatically switches to the FRC oscillator and
the user can switch to the desired crystal oscillator in
the Trap Service Routine.
2009 Microchip Technology Inc.
POR
MCLR
WDT
Software
Illegal Opcode
Uninitialized W
Trap Conflict
Note 1:
crystal oscillator is used).
Reset Type
2:
3:
4:
5:
6:
T
T
Power-up Timer delay (if regulator is disabled). T
states, including waking from Sleep mode, only if the regulator is enabled.
T
T
oscillator clock to the system.
T
T
POR AND LONG OSCILLATOR
START-UP TIMES
FAIL-SAFE CLOCK MONITOR
(FSCM) AND DEVICE RESETS
STARTUP
OST
RST
POR
LOCK
FSCM
= Internal state Reset time (20 s nominal).
= Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the
= Power-on Reset delay (10 s nominal).
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
= PLL lock time (20 s nominal).
= Fail-Safe Clock Monitor delay (100 s nominal).
EC, FRC, LPRC
ECPLL, FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
Any Clock
Any Clock
Any clock
Any Clock
Any Clock
Any Clock
Clock Source
= Conditional POR delay of 20 s nominal (if on-chip regulator is enabled) or 64 ms nominal
PIC24HJXXXGPX06A/X08A/X10A
T
T
T
T
POR
POR
POR
POR
SYSRST Delay
+ T
+ T
+ T
+ T
Preliminary
STARTUP
STARTUP
STARTUP
STARTUP
T
T
T
T
T
T
RST
RST
RST
RST
RST
RST
STARTUP
+ T
+ T
+ T
+ T
6.2.2.1
When the system clock source is provided by a crystal
oscillator and/or the PLL, a small delay, T
matically inserted after the POR and PWRT delay
times. The FSCM does not begin to monitor the system
clock source until this delay expires. The FSCM delay
time is nominally 500 s and provides additional time
for the oscillator and/or PLL to stabilize. In most cases,
the FSCM delay prevents an oscillator failure trap at a
device Reset when the PWRT is disabled.
6.3
Most of the Special Function Registers (SFRs) associ-
ated with the CPU and peripherals are reset to a
particular value at a device Reset. The SFRs are
grouped by their peripheral or CPU function and their
Reset values are specified in each section of this
manual.
The Reset value for each SFR does not depend on the
type of Reset, with the exception of two registers. The
Reset value for the Reset Control register, RCON,
depends on the type of device Reset. The Reset value
for the Oscillator Control register, OSCCON, depends
on the type of Reset and the programmed values of the
oscillator Configuration bits in the FOSC Configuration
register.
RST
RST
RST
RST
is also applied to all returns from powered-down
Special Function Register Reset
States
System Clock
T
OST
FSCM Delay for Crystal and PLL
Clock Sources
T
Delay
T
LOCK
OST
+ T
—
—
—
—
—
—
—
LOCK
FSCM
T
T
T
Delay
FSCM
FSCM
FSCM
—
—
—
—
—
—
—
DS70592B-page 71
1, 2, 3
1, 2, 3, 5, 6
1, 2, 3, 4, 6
1, 2, 3, 4, 5, 6
3
3
3
3
3
3
FSCM
Notes
, is auto-
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