PIC24HJ12GP202-E/ML Microchip Technology, PIC24HJ12GP202-E/ML Datasheet - Page 165

• Manufacturer Part Number: PIC24HJ12GP202-E/ML
• Description: 12KB, Flash, 1024bytes-RAM, 40MIPS, 21I/O, 16-bit Family,nanoWatt 28 QFN 6x6mm T
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ12GP202-E/ML

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.0
PIC24HJ12GP201/202 devices include several fea-
tures intended to maximize application flexibility and
reliability, and minimize cost through elimination of
external components. These are:
• Flexible configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit emulation
TABLE 19-1:
© 2009 Microchip Technology Inc.
0xF80000
0xF80002
0xF80004
0xF80006
0xF80008
0xF8000A
0xF8000C FPOR
0xF8000E
0xF80010
0xF80012
0xF80014
0xF80016
Note 1:
Note:
programming capability
Address
SPECIAL FEATURES
Reserved bits read as ‘1’ and must be programmed as ‘1’.
This data sheet summarizes the features
of the PIC24HJ12GP201/202 devices. It is
not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
“PIC24H
Please see the Microchip web site
(www.microchip.com) for the latest family
reference manual sections.
FBS
Reserved
FGS
FOSCSEL
FOSC
FWDT
FICD
FUID0
FUID1
FUID2
FUID3
Name
DEVICE CONFIGURATION REGISTER MAP
Family
FWDTEN
IESO
Bit 7
FCKSM<1:0>
—
—
—
Reserved
Reference
WINDIS
(1)
Bit 6
—
—
—
—
Manual”.
IOL1WAY
JTAGEN
Preliminary
Bit 5
—
—
—
—
—
PIC24HJ12GP201/202
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
19.1
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select
various device configurations. These bits are mapped
starting at program memory location 0xF80000.
The Device Configuration register map is shown in
Table 19-1.
The individual Configuration bit descriptions for the
FBS, FGS, FOSCSEL, FOSC, FWDT, FPOR, and
FICD Configuration registers are shown in Table 19-
2.
Note that address 0xF80000 is beyond the user program
memory space. It belongs to the configuration memory
space (0x800000-0xFFFFFF), which can only be
accessed using table reads and table writes.
The upper byte of all device Configuration registers
should always be ‘1111
appear to be NOP instructions in the remote event that
their locations are ever executed by accident. Since
Configuration bits are not implemented in the
corresponding locations, writing ‘1’s to these locations
has no effect on device operation.
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires that power to the device
be cycled.
WDTPRE
ALTI2C
Reserved
Bit 4
—
—
—
—
Configuration Bits
—
(1)
Bit 3
—
—
—
—
BSS<2:0>
OSCIOFNC POSCMD<1:0>
WDTPOST<3:0>
Bit 2
1111’. This makes them
—
GSS<1:0>
FPWRT<2:0>
FNOSC<2:0>
DS70282D-page 163
Bit 1
ICS<1:0>
GWRP
BWRP
Bit 0