PIC24HJ12GP202-E/ML Microchip Technology, PIC24HJ12GP202-E/ML Datasheet - Page 61

• Manufacturer Part Number: PIC24HJ12GP202-E/ML
• Description: 12KB, Flash, 1024bytes-RAM, 40MIPS, 21I/O, 16-bit Family,nanoWatt 28 QFN 6x6mm T
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ12GP202-E/ML

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.3
PIC24HJ12GP201/202 devices implement a total of 17
registers for the interrupt controller:
• Interrupt Control Register 1 (INTCON1)
• Interrupt Control Register 2 (INTCON2)
• Interrupt Flag Status Registers (IFSx)
• Interrupt Enable Control Registers (IECx)
• Interrupt Priority Control Registers (IPCx)
• Interrupt Control and Status Register (INTTREG)
7.3.1
Global interrupt control functions are controlled from
INTCON1 and INTCON2. INTCON1 contains the
Interrupt Nesting Disable (NSTDIS) bit as well as the
control and status flags for the processor trap sources.
The INTCON2 register controls the external interrupt
request signal behavior and the use of the Alternate
Interrupt Vector Table.
7.3.2
The IFS registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal and
is cleared via software.
7.3.3
The IEC registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
© 2009 Microchip Technology Inc.
Interrupt Control and Status
Registers
INTCON1 AND INTCON2
IFSx
IECx
Preliminary
PIC24HJ12GP201/202
7.3.4
The IPC registers are used to set the interrupt priority
level for each source of interrupt. Each user interrupt
source can be assigned to one of eight priority levels.
7.3.5
The INTTREG register contains the associated
interrupt vector number and the new CPU interrupt
priority level, which are latched into vector number
(VECNUM<6:0>) and interrupt level (ILR<3:0>) bit
fields in the INTTREG register. The new interrupt
priority level is the priority of the pending interrupt.
The interrupt sources are assigned to the IFSx, IECx,
and IPCx registers in the same sequence that they are
listed in Table 7-1. For example, the INT0 (External
Interrupt 0) is shown as having vector number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0<0>, the INT0IE bit in IEC0<0>, and the INT0IP
bits in the first positions of IPC0 (IPC0<2:0>).
7.3.6
Although they are not specifically part of the interrupt
control hardware, two of the CPU Control registers
contain bits that control interrupt functionality:
• The CPU STATUS register, SR, contains the
• The CORCON register contains the IPL3 bit
All Interrupt registers are described in Register 7-1
through Register 7-19 in the following pages.
IPL<2:0> bits (SR<7:5>). These bits indicate the
current CPU interrupt priority level. The user can
change the current CPU priority level by writing to
the IPL bits.
which, together with IPL<2:0>, also indicates the
current CPU priority level. IPL3 is a read-only bit,
so that trap events cannot be masked by the user
software.
IPCx
INTTREG
STATUS REGISTERS
DS70282D-page 59