PIC24HJ12GP202-E/SO Microchip Technology, PIC24HJ12GP202-E/SO Datasheet - Page 54

• Manufacturer Part Number: PIC24HJ12GP202-E/SO
• Description: 12KB, Flash, 1024bytes-RAM, 40MIPS, 21I/O, 16-bit Family,nanoWatt 28 SOIC .300in
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ12GP202-E/SO

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164339 - MODULE SKT FOR PM3 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC24HJ12GP201/202
6.2
A POR circuit ensures the device is reset from power-
on. The POR circuit is active until V
V
delay T
become stable.
The device supply voltage characteristics must meet
the
requirements to
Section 22.0 “Electrical Characteristics” for details.
The POR status (POR) bit in the Reset Control
(RCON<0>) register is set to indicate the Power-on
Reset.
FIGURE 6-3:
DS70282D-page 52
POR
SYSRST
SYSRST
SYSRST
specified
threshold and the delay T
POR
POR
V
V
V
DD
DD
DD
ensures the internal device bias circuits
starting
V
DD
generate
dips before PWRT expires
BROWN-OUT SITUATIONS
voltage
the
POR
POR.
has elapsed. The
and
DD
crosses the
rise
Refer
rate
Preliminary
to
T
BOR
+ T
T
T
PWRT
BOR
BOR
6.3
The on-chip regulator has a BOR circuit that resets the
device when the V
device operation. The BOR circuit keeps the device in
Reset until V
T
regulator output becomes stable.
The BOR status (BOR) bit in the Reset Control
(RCON<1>) register is set to indicate the Brown-out
Reset.
The device will not run at full speed after a BOR as the
V
operation. The PWRT provides power-up time delay
(T
stabilized at the appropriate levels for full-speed
operation before the SYSRST is released.
The power-up timer delay (T
the
(FPWRT<2:0>)
(FPOR<2:0>) register, which provides eight settings
(from 0 ms to 128 ms). Refer to Section 19.0 “Special
Features” for further details.
Figure 6-3 shows the typical brown-out scenarios. The
Reset delay (T
rises above the V
BOR
DD
+ T
PWRT
+ T
PWRT
should rise to acceptable levels for full-speed
PWRT
has elapsed. The delay T
Power-on
) to ensure that the system power supplies have
BOR and PWRT
DD
BOR
crosses V
BOR
bits
DD
+ T
Reset
is too low (V
trip point.
PWRT
in
© 2009 Microchip Technology Inc.
BOR
) is initiated each time V
the
V
V
PWRT
V
Timer
BOR
BOR
BOR
threshold and the delay
BOR
DD
POR
) is programmed by
ensures the voltage
< V
Value
BOR
Configuration
) for proper
Select
DD