S29AL008J55TFIR20 Spansion Inc., S29AL008J55TFIR20 Datasheet - Page 16
![no-image](/images/manufacturer_photos/0/6/621/spansion_inc__sml.jpg)
S29AL008J55TFIR20
Manufacturer Part Number
S29AL008J55TFIR20
Description
IC 8M FLASH MEMORY
Manufacturer
Spansion Inc.
Datasheet
1.S29AL008J55TFIR20.pdf
(56 pages)
Specifications of S29AL008J55TFIR20
Cell Type
NOR
Density
8Mb
Access Time (max)
55ns
Interface Type
Parallel
Boot Type
Bottom
Address Bus
20/19Bit
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Package Type
TSOP
Program/erase Volt (typ)
3 to 3.6V
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
1M/512K
Supply Current
12mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S29AL008J55TFIR20
Manufacturer:
SPANSION
Quantity:
20 000
7.6
7.7
16
Automatic Sleep Mode
RESET#: Hardware Reset Pin
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for t
CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the system. I
Characteristics on page 40
The RESET# pin provides a hardware method of resetting the device to reading array data. When the system
drives the RESET# pin to V
progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state machine to reading array data. The operation that was
interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure
data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at V
draws CMOS standby current (I
current will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the
internal reset operation is complete, which requires a time of t
system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not executing (RY/BY# pin is 1), the reset operation is
completed within a time of t
RESET# pin returns to V
Refer to the tables in
for the timing diagram.
AC Characteristics on page 42
IH
.
IL
READY
represents the automatic sleep mode current specification.
for at least a period of t
CC4
(not during Embedded Algorithms). The system can read data t
). If RESET# is held at V
S29AL008J
D a t a
ACC
+ 30 ns. The automatic sleep mode is independent of the
RP
for RESET# parameters and to
, the device immediately terminates any operation in
S h e e t
IL
READY
but not within V
(during Embedded Algorithms). The
S29AL008J_00_09 February 23, 2010
SS
±0.3/0.1 V, the standby
Figure 17.2 on page 43
SS
±0.3 V, the device
CC4
in the
RH
after the
DC