S29JL032J70TFI420 Spansion Inc., S29JL032J70TFI420 Datasheet

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S29JL032J 32 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory Data Sheet (Preliminary) Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein ...

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... Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” ...

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S29JL032J 32 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory Data Sheet (Preliminary) Distinctive Characteristics Architectural Advantages  Simultaneous Read/Write operations – Data can be continuously read from one bank while executing erase/program ...

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S29JL032J S29JL032J_00_03 August 25, 2010 ...

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Table of Contents Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Zero-Power Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Figures Figure 8.1 Temporary Sector Unprotect Operation ...

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Tables Table 8.1 S29JL032J Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into separate banks (see form user-defined bank groups. During an Erase/Program operation, any of the non-busy banks ...

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Product Selector Guide Speed Option Max Access Time (ns), t ACC CE# Access (ns OE# Access (ns Block Diagram 3.1 4-Bank Device Mux A20–A0 RY/BY# A20–A0 STATE RESET# CONTROL WE# ...

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3.2 2-Bank Device A20–A0 RY/BY# A20–A0 RESET# STATE CONTROL WE# & CE# COMMAND BYTE# REGISTER WP#/ACC DQ15–DQ0 A20–A0 August 25, 2010 S29JL032J_00_03 ...

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Connection Diagrams 4.1 48-pin TSOP Package A15 A14 A13 A12 A11 A10 A19 A20 WE# RESET# WP#/ACC RY/BY# A18 A17 4.2 48-ball FBGA Package ...

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Pin Description A20–A0 DQ14–DQ0 DQ15/A-1 CE# OE# WE# WP#/ACC RESET# BYTE# RY/BY Logic Symbol August 25, 2010 S29JL032J_00_03 ...

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Ordering Information The order number (Valid Combination) is formed by the following: S29JL032J 60 Device Family S29JL032J 3.0 Volt-only, 32 Mbit ( 16-Bit 8-Bit) Simultaneous Read/Write Flash Memory Manufactured on 110 nm process technology Device ...

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Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The ...

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Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to V control and selects the device. OE# is the output control and gates array data to the ...

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8.4 Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in another bank of memory. An erase operation may also be suspended to ...

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Output Disable Mode When the OE# input impedance state. Device Bank 1 Model Number Mbit 01 Mbit Device Model Number Mbits 21 Mbit 31 Mbit 41 Mbit 18 ...

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Table 8.3 S29JL032J Sector Addresses - Top Boot Devices (Sheet Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 ...

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Table 8.3 S29JL032J Sector Addresses - Top Boot Devices (Sheet Sector SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 ...

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Table 8.4 S29JL032J Sector Addresses - Bottom Boot Devices (Sheet Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 ...

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Table 8.4 S29JL032J Sector Addresses - Bottom Boot Devices (Sheet Sector SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 ...

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8.9 Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be ...

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Boot Sector/Sector Block Protection and Unprotection Note: For the following discussion, the term “sector” applies to both boot sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the ...

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Sector SA70 SA69-SA67 SA66-SA63 SA62-SA59 SA58-SA55 SA54-SA51 SA50-SA47 SA46-SA43 SA42-SA39 SA38-SA35 SA34-SA31 SA30-SA27 SA26-SA23 SA22-SA19 SA18-SA15 SA14-SA11 SA10-SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 Sector Protect/Sector Unprotect requires V system or via programming equipment. ...

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Write Protect (WP#) The Write Protect function provides a hardware method of protecting certain boot sectors without using V This function is one of two provided by the WP#/ACC pin. If the system asserts V outermost 8 Kbyte boot ...

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START PLSCNT = 1 RESET Wait First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with A6 = ...

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Secured Silicon Region The Secured Silicon Region feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Region is 256 bytes in length, and may shipped unprotected, allowing customers ...

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8.14 Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to hardware data protection measures prevent accidental erasure or programming, which might otherwise be ...

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Common Flash Memory Interface (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, ...

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Addresses Addresses (Word Mode) (Byte Mode) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch August 25, 2010 S29JL032J_00_03 ...

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Addresses Addresses (Word Mode) (Byte Mode) 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 57h 58h 59h 5Ah 5Bh ...

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10. Command Definitions Writing specific address and data sequences into the command register initiates device operations. Table 10.1 on page 39 values or writing them in the improper sequence may place the device in an unknown ...

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Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a ...

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10.5.1 Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by ...

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Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the ...

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Notes: 1. See Table 10.1 on page 39 2. See DQ3: Sector Erase Timer on page 44 August 25, 2010 S29JL032J_00_03 ...

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Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when ...

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Command Sequence (Note 1) Addr Read (Note Reset (Note 7) 1 XXX Word 555 Manufacturer ID 4 Byte AAA Word 555 Device ID (Note 9) 6 Byte AAA Word 555 Secured Silicon Region ...

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The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 12. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 13. The Unlock Bypass Reset command is required to ...

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Notes Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. ...

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During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. After ...

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11.4 DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector ...

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DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors ...

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12. Absolute Maximum Ratings Storage Temperature, Plastic Packages Ambient Temperature with Power Applied Voltage with Respect to Ground and RESET# (Note 2) WP#/ACC All other pins (Note 1) Output Short Circuit Current Notes: 1. ...

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Operating Ranges Industrial (I) Devices Ambient Temperature (T V Supply Voltages CC V for standard voltage range CC Operating ranges define those limits between which the functionality of the device is guaranteed. 14. DC Characteristics 14.1 CMOS Compatible Parameter ...

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14.2 Zero-Power Flash Figure 14.1 I CC1 500 Note: Addresses are switching at 1 MHz Note 25°C August 25, ...

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Test Conditions Note: Diodes are IN3064 or equivalent. Output Load Capacitance, C Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels Note: 1. Input rise and fall times are 0-100%. ...

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17. AC Characteristics 17.1 Read-Only Operations Parameter JEDEC Std Read Cycle Time AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output ...

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Hardware Reset (RESET#) Parameter JEDEC Std t Ready t Ready RPD t RB Note: Not 100% tested. RY/BY# CE#, OE# RESET# RY/BY# CE#, OE# RESET ...

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17.3 Word/Byte Configuration (BYTE#) Parameter JEDEC Std ELFL/ ELFH t FLQZ t FHQV BYTE# DQ14–DQ0 Switching from word to byte mode BYTE# Switching DQ14–DQ0 from byte to word mode CE# WE# BYTE# Note: Refer ...

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Erase and Program Operations Parameter JEDEC Std t t AVAV AVWL AS t ASO t t WLAX AH t AHT t t DVWH WHDX DH t OEPH t t GHWL GHWL t t ...

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Addresses CE# OE# WE# Data RY/BY VCS Notes program address program data Illustration shows device in word mode WP#/ACC August ...

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Addresses CE# OE# WE# Data RY/BY# t VCS V CC Notes sector address (for Sector Erase Valid Address for reading status data (see 2. These waveforms are for the word mode. Figure 17.8 Back-to-back Read/Write ...

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Figure 17.9 Data# Polling Timings (During Embedded Algorithms Addresses VA t ACC OEH WE# DQ7 DQ0–DQ6 t BUSY RY/BY# Note Valid address. Illustration ...

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Enter Erase Embedded Suspend Erasing Erase Erase Suspend WE# DQ6 DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6. 17.5 Temporary Sector Unprotect ...

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Figure 17.13 Sector/Sector Block Protect and Unprotect Timing Diagram RESET# SA, A6, A1, A0 Sector Group Protect/Unprotect Data 60h 1 µs CE# WE# OE# Note: *For sector protect ...

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Figure 17.14 Alternate CE# Controlled Write (Erase/Program) Operation Timings Addresses WE# OE# CE# Data RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation program address sector address, PD ...

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18. Erase and Programming Performance Parameter Sector Erase Time Chip Erase Time Byte Program Time Word Program Time Accelerated Byte/Word Program Time Notes: 1. Typical program and erase times assume the following conditions: 25° ...

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Physical Dimensions 20.1 TS 048—48-Pin Standard TSOP STANDARD PIN OUT (TOP VIEW SEE DETAIL 0. (N/2 TIPS) PARALLEL TO SEATING PLANE TS/TSR 048 Package Jedec MO-142 (D) DD Symbol MIN NOM ...

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20.2 VBK048—48-Pin FBGA PACKAGE VBK 048 JEDEC 8. 6.15 mm NOM PACKAGE SYMBOL MIN A --- A1 0.18 D 8.15 BSC. E 6.15 BSC. D1 5.60 BSC. E1 4.00 BSC φb ...

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Revision History Section Revision 01 (January 27, 2010) Initial release. Revision 02 (June 15, 2010) Changed all references to typical Sector Erase time from 0.4 sec to 0.5 sec. Global Changed all references to “Secured Silicon Sector” to “Secured ...

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Section Changed section title from "TSOP Pin Capacitance" to "Pin Capacitance". Updated values to reflect maximum capacitances for both TSOP and BGA. Pin Capacitance Removed typical capacitance values. Added specific pin clarifications to parameter descriptions. Physical ...

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... Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2010 Spansion Inc. All rights reserved. Spansion and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners ...