SST25VF064C-80-4C-Q2AE Microchip Technology, SST25VF064C-80-4C-Q2AE Datasheet
SST25VF064C-80-4C-Q2AE
Specifications of SST25VF064C-80-4C-Q2AE
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SST25VF064C-80-4C-Q2AE Summary of contents
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... Erase or Program operation is less than alternative flash memory technolo- gies. The SST25VF064C device is offered in 16-lead SOIC (300 mils), 8-contact WSON (6mm x 8mm), and 8-lead SOIC (200 mils) packages. See Figure 2 for pin assignments. The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc. ...
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... Latches CE# FIGURE 1: Functional Block Diagram ©2010 Silicon Storage Technology, Inc. 64 Mbit SPI Serial Dual I/O Flash X - Decoder Control Logic Serial Interface SCK SI/SIO SO/SIO WP# RST#/HOLD SST25VF064C SuperFlash Memory Y - Decoder Page Buffer, I/O Buffers and Data Latches 1392 B1.0 S71392-04-000 04/10 ...
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... Mbit SPI Serial Dual I/O Flash SST25VF064C PIN DESCRIPTION RST#/HOLD Top View CE# SO/SIO 1 FIGURE 2: Pin Assignments for 16-Lead SOIC, 8-Contact WSON, and 8-Lead SOIC TABLE 1: Pin Description Symbol Pin Name SCK Serial Clock SI Serial Data Input SO Serial Data Output SIO[0:1] ...
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... FIGURE 3: SPI Protocol ©2010 Silicon Storage Technology, Inc. 64 Mbit SPI Serial Dual I/O Flash The SST25VF064C supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred ...
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... Mbit SPI Serial Dual I/O Flash SST25VF064C Reset/Hold Mode The RST#/HOLD# pin provides either a hardware reset or a hold pin. From power-on, the RST#/HOLD# pin defaults as a hardware reset pin (RST#). The Hold mode for this pin is a user selected option where an EHLD instruction enables the Hold mode ...
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... Hold timing. Hold Active Hold Security ID SST25VF064C offers a 256-bit Security ID (Sec ID) fea- ture. The Security ID space is divided into two parts – one factory-programmed, 64-bit segment and one user-pro- grammable 192-bit segment. The factory-programmed segment is programmed at SST with a unique number and cannot be changed ...
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... Mbit SPI Serial Dual I/O Flash SST25VF064C Status Register The software status register provides status on whether the flash memory array is available for any Read or Write oper- ation, whether the device is Write enabled, and the state of the Memory Write protection. During an internal Erase or ...
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... FOR 1 Status Register Bit BP3 BP2 BP1 BP0 SST25VF064C ), enables the Block-Protection the BPL bit has no IH Protected Memory Address 64 Mbit None 7F0000H-7FFFFFH 7E0000H-7FFFFFH 7C0000H-7FFFFFH 780000H-7FFFFFH 700000H-7FFFFFH 600000H-7FFFFFH 400000H-7FFFFFH 000000H-7FFFFFH 000000H-7FFFFFH 000000H-7FFFFFH 000000H-7FFFFFH 000000H-7FFFFFH 000000H-7FFFFFH 000000H-7FFFFFH 000000H-7FFFFFH T5.0 1392 S71392-04-000 04/10 ...
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... Mbit SPI Serial Dual I/O Flash SST25VF064C INSTRUCTIONS Instructions are used to read, write (Erase and Program), and configure the SST25VF064C. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. The Write-Enable (WREN) instruction must be executed prior any Page-Program, Dual-Input Page-Pro- gram, Sector-Erase, Block-Erase, Write-Status-Register, Chip-Erase, Program SID, or Lockout SID instructions ...
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... The Read instruction is initiated by executing an 8-bit com- mand, 03H, followed by address bits A remain active low for the duration of the Read cycle. See Figure 6 for the Read sequence ADD. ADD. ADD. MSB N D OUT MSB 10 SST25VF064C IH IH CE# must N+1 N+2 N+3 ...
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... Mbit SPI Serial Dual I/O Flash SST25VF064C CE# MODE SCK MODE HIGH IMPEDANCE SO FIGURE 7: High-Speed Read Sequence Fast-Read Dual-Output (75 MHz) The Fast-Read Dual-Output (3BH) instruction outputs data MHz from the SIO and SIO 0 instruction, execute an 8-bit command (3BH) followed by address bits A23-A0 and a dummy byte on SI/SIO ...
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... For example, once the data from address location 7FFFFFH is read, the next output is from address location 000000H. See Figure 9 for the Fast-Read Dual I/o sequence Dummy Cycle A23-16 A15-8 A7-0 12 SST25VF064C and SIO lines. SIO outputs, per IO, Switches from Input to Output DOUT DOUT DOUT DOUT ...
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... PP Program operation. See Figure 10 for the Page-Program sequence. For Page-Program, the memory range for SST25VF064C is set in 256 byte page boundaries. The device handles shifting of more than 256 bytes of data by keeping the last 256 bytes of data shifted as the correct data to be pro- grammed ...
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... TPP for the completion of the internal self-timed Page- Program operation. See Figure 10 for the Dual-Input-Page- Program sequence. For Dual-Input Page-Program, the memory range for the SST25VF064C is set in 256 byte page boundaries. The device handles shifting of more than 256 bytes of data by pins. CE# must be 0 keeping the last 256 bytes of data shifted as the correct data to be programmed ...
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... Mbit SPI Serial Dual I/O Flash SST25VF064C Sector-Erase The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any command sequence ...
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... ADDR ADDR MSB MSB HIGH IMPEDANCE ADDR ADDR MSB MSB HIGH IMPEDANCE 16 SST25VF064C ), remaining address bits can X CE# must be driven high before the instruction -A . Address bits A -A are used remaining address bits can X CE# must be driven high before the instruction 23 24 ...
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... Mbit SPI Serial Dual I/O Flash SST25VF064C Chip-Erase The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence ...
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... Write-Status-Register (WRSR) instruction; however, the Write-Enable-Latch bit in the Status Register will be cleared upon the rising edge CE# of the WRSR instruction. CE# must be driven high before the WREN instruction is executed. CE# MODE SCK MODE MSB HIGH IMPEDANCE SO 1392 F18.0 18 SST25VF064C Status 1392 F17.0 S71392-04-000 04/10 ...
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... Mbit SPI Serial Dual I/O Flash SST25VF064C Write-Disable (WRDI) The Write-Disable (WRDI) instruction resets the Write- Enable-Latch bit to ‘0,’ thereby, preventing any new Write operations. The WRDI instruction will not terminate any program or erase operation in progress. Any program or FIGURE 18: Write Disable (WRDI) Sequence © ...
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... BPL bit to ‘1’ to lock down the status register as well as altering the BP0, BP1, BP2, and BP3 bits at the same time. See Table 3 for a summary descrip- tion of WP# and BPL functions MODE 3 MODE 0 STATUS REGISTER MSB MSB HIGH IMPEDANCE 20 SST25VF064C ) prior to the low- IH 1392 F20.0 S71392-04-000 04/10 ...
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... Enable-Hold FIGURE 20: Enable-Hold Sequence Read-ID (RDID) The Read-ID instruction (RDID) identifies the device as SST25VF064C and manufacturer as SST. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits A Read-ID instruction, the manufacturer’ located in address 00000H and the device ID is located in address 00001H ...
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... Data Sheet JEDEC Read-ID The JEDEC Read-ID instruction identifies the device as SST25VF064C and the manufacturer as SST. The device information can be read from executing the 8-bit command, 9FH. Following the JEDEC Read-ID instruction, the 8-bit manufacturer’s ID, BFH, is output from the device. After that, a 24-bit device ID is shifted out on the SO pin ...
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... Mbit SPI Serial Dual I/O Flash SST25VF064C ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability. Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55° ...
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... MHz 50 MHz Min Max Min 0.1 0.1 0.1 0 2.5 1.0 and T requirements SCKH SCKL 24 SST25VF064C Units Test Method Cycles JEDEC Standard A117 Years JEDEC Standard A103 mA JEDEC Standard 78 T12.0 1392 75/80 MHz Max Min Max Units 50 75/80 MHz 0.1 V/ns 0.1 V/ ...
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... Mbit SPI Serial Dual I/O Flash SST25VF064C CE# T CES T CHH SCK T DS MSB SI HIGH-Z SO FIGURE 23: Serial Input Timing Diagram CE# T SCKH SCK T CLZ SO SI FIGURE 24: Serial Output Timing Diagram CE# SCK SO SI HOLD# FIGURE 25: Hold Timing Diagram ©2010 Silicon Storage Technology, Inc. ...
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... Silicon Storage Technology, Inc. 64 Mbit SPI Serial Dual I/O Flash ramp rate of greater than 1V per 100 ms ( PU-READ V min parameter. RECR T PU-READ Device fully accessible T PU-WRITE 26 SST25VF064C Minimum Units 100 µs 100 µs T14.0 1392 T RECR 1203 F37.0 Time 1392 F26.0 S71392-04-000 04/10 ...
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... Mbit SPI Serial Dual I/O Flash SST25VF064C V IHT INPUT V ILT AC test inputs are driven at V (0.9V IHT for inputs and outputs are V (0.6V HT FIGURE 28: AC Input/Output Reference Waveforms ©2010 Silicon Storage Technology, Inc REFERENCE POINTS for a logic “1” and V (0.1V ...
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... Minimum Endurance 4 = 10,000 cycles Operating Frequency MHz Version C = Page-Program Device Density 064 = 64 Mbit Voltage V = 2.7-3.6V Product Series 25 = Serial Peripheral Interface flash memory 1. Environmental suffix “E” denotes non-Pb solder. SST non-Pb solder devices are “RoHS Compliant”. SST25VF064C-80-4C-Q2AE 28 SST25VF064C S71392-04-000 04/10 ...
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... Mbit SPI Serial Dual I/O Flash SST25VF064C PACKAGING DIAGRAMS Pin #1 Identifier 10.08 10.50 7° 4 places .33 .51 Note: 1. Complies with JEDEC publication 95 MS-013 AA dimensions (except as noted), although some dimensions may be more stringent. † = JEDEC min is 10.10; SST min (10.08) is less stringent ‡ = JEDEC min is 0.40; SST min (0.38) is less stringent 2. All linear dimensions are in metric (min/max). 3. Coplanarity: 0.1 (± ...
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... SST Package Code: Q2A ©2010 Silicon Storage Technology, Inc. 64 Mbit SPI Serial Dual I/O Flash SIDE VIEW 0.2 6.00 ±0.10 A 0.05 Max 0.80 0. the unit SST25VF064C BOTTOM VIEW Pin #1 1.27 BSC 4.8 0.45 0.35 6.0 A 0.55 0.45 CROSS SECTION Detail A-A 0.80 ...
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... Mbit SPI Serial Dual I/O Flash SST25VF064C TOP VIEW Pin #1 Identifier 5.38 5.18 8.10 7.70 Note: 1. All linear dimensions are in millimeters (max/min). 2. Coplanarity: 0 Maximum allowable mold flash is 0. the package ends and 0.25 mm between leads. FIGURE 31: 8-Lead Small Outline Integrated Circuit (SOIC) ...