SST25VF064C-80-4C-Q2AE Microchip Technology, SST25VF064C-80-4C-Q2AE Datasheet - Page 20

• Manufacturer Part Number: SST25VF064C-80-4C-Q2AE
• Description: 2.7V To 3.6V 64Mbit SPI Serial Flash 8 TDFN 6x8x0.8mm TRAY
• Manufacturer: Microchip Technology

Specifications of SST25VF064C-80-4C-Q2AE

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 64M (8M x 8)
• Speed: 80MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-WDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Sheet
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction
arms the Write-Status-Register (WRSR) instruction and
opens the status register for alteration. The Write-Status-
Register instruction must be executed immediately after the
execution of the Enable-Write-Status-Register instruction.
This two-step instruction sequence of the EWSR instruc-
Write-Status-Register (WRSR)
The Write-Status-Register instruction writes new values to
the BP3, BP2, BP1, BP0, and BPL bits of the status regis-
ter. CE# must be driven low before the command
sequence of the WRSR instruction is entered and driven
high before the WRSR instruction is executed. See Figure
19 for EWSR or WREN and WRSR instruction sequences.
Executing the Write-Status-Register instruction will be
ignored when WP# is low and BPL bit is set to ‘1’. When
the WP# is low, the BPL bit can only be set from ‘0’ to ‘1’ to
lock-down the status register, but cannot be reset from ‘1’ to
‘0’. When WP# is high, the lock-down function of the BPL
©2010 Silicon Storage Technology, Inc.
FIGURE 19: Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and Write-Status-Register
SCK
CE#
SO
SI
MODE 3
MODE 0
(WRSR) Sequence
0 1 2 3 4 5 6 7
MSB
50 or 06
HIGH IMPEDANCE
MODE 3
MODE 0
20
MSB
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
tion followed by the WRSR instruction works like software
data protection (SDP) command structure which prevents
any accidental alteration of the status register values. CE#
must be driven low before the EWSR instruction is entered
and must be driven high before the EWSR instruction is
executed.
bit is disabled and the BPL, BP0, BP1, BP2, and BP3 bits
in the status register can all be changed. As long as BPL bit
is set to ‘0’ or WP# pin is driven high (V
to-high transition of the CE# pin at the end of the WRSR
instruction, the bits in the status register can all be altered
by the WRSR instruction. In this case, a single WRSR
instruction can set the BPL bit to ‘1’ to lock down the status
register as well as altering the BP0, BP1, BP2, and BP3
bits at the same time. See Table 3 for a summary descrip-
tion of WP# and BPL functions.
01
64 Mbit SPI Serial Dual I/O Flash
MSB
7 6 5 4 3 2 1 0
REGISTER IN
STATUS
SST25VF064C
1392 F20.0
IH
S71392-04-000
) prior to the low-
04/10