SST25VF080B-80-4I-QAE Microchip Technology, SST25VF080B-80-4I-QAE Datasheet - Page 6
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SST25VF080B-80-4I-QAE
Manufacturer Part Number
SST25VF080B-80-4I-QAE
Description
2.7V To 3.6V 8Mbit SPI Serial Flash 8 TDFN-S 6x5x0.8mm TUBE
Manufacturer
Microchip Technology
Specifications of SST25VF080B-80-4I-QAE
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
8M (1M x 8)
Speed
80MHz
Interface
SPI Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-WSON
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
A Microchip Technology Company
©2011 Silicon Storage Technology, Inc.
Hold Operation
Write Protection
Write Protect Pin (WP#)
The HOLD# pin is used to pause a serial sequence underway with the SPI flash memory without reset-
ting the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD#
mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The
HOLD mode ends when the HOLD# signal’s rising edge coincides with the SCK active low state.
If the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device
enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK active low state, then the device exits in Hold mode
when the SCK next reaches the active low state. See Figure 4 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-impedance state while SI and SCK can be V
If CE# is driven active high during a Hold condition, it resets the internal logic of the device. As long as
HOLD# signal is low, the memory remains in the Hold condition. To resume communication with the device,
HOLD# must be driven active high, and CE# must be driven active low. See Figure 24 for Hold timing.
Figure 4: Hold Condition Waveform
SST25VF080B provides software Write protection. The Write Protect pin (WP#) enables or disables
the lock-down function of the status register. The Block-Protection bits (BP3, BP2, BP1, BP0, and BPL)
in the status register provide Write protection to the memory array and the status register. See Table 4
for the Block-Protection description.
The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register.
When WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined by
the value of the BPL bit (see Table 2). When WP# is high, the lock-down function of the BPL bit is disabled.
Table 2: Conditions to execute Write-Status-Register (WRSR) Instruction
HOLD#
SCK
WP#
H
L
L
Active
BPL
X
1
0
6
Hold
Execute WRSR Instruction
Not Allowed
Allowed
Allowed
8 Mbit SPI Serial Flash
Active
Hold
SST25VF080B
S71296-05-000
Active
1296 HoldCond.0
Data Sheet
IL
T2.0 1296
or V
02/11
IH.