STK11C68-SF25 Cypress Semiconductor Corp, STK11C68-SF25 Datasheet - Page 5

• Manufacturer Part Number: STK11C68-SF25
• Description: STK11C68-SF25
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of STK11C68-SF25

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 64K (8K x 8)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (8.69mm width)
• Word Size: 8b
• Organization: 8Kx8
• Density: 64Kb
• Interface Type: Parallel
• Access Time (max): 25ns
• Operating Supply Voltage (typ): 5V
• Package Type: SOIC
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 70C
• Pin Count: 28
• Mounting: Surface Mount
• Supply Current: 90mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The overall average current drawn by the STK11C68 depends
on the following items:
■
■
■
■
■
■
■
Figure 2. Current Versus Cycle Time (Read)
Figure 3. Current Versus Cycle Time (Write)
Table 1. Hardware Mode Selection
Document Number: 001-50638 Rev. *A
Note
1. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.
The duty cycle of chip enable
The overall cycle rate for accesses
The ratio of Reads to Writes
CMOS versus TTL input levels
The operating temperature
The V
I/O loading
CC
CE
L
L
level
WE
H
H
A12–A0
0x0AAA
0x0AAA
0x1FFF
0x10F0
0x0F0F
0x1FFF
0x10F0
0x0F0E
0x0000
0x1555
0x0000
0x1555
Nonvolatile RECALL
Nonvolatile STORE
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease of use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■
■
■
The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprograms these values. Final NV patterns
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.
The end product’s firmware should not assume that an NV array
is in a set programmed state. Routines that check memory
content values to determine first time system configuration,
cold or warm boot status, and so on must always program a
unique NV pattern (for example, complex 4-byte pattern of 46
E6 49 53 hex or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
Power up boot firmware routines should rewrite the nvSRAM
into the desired state. While the nvSRAM is shipped in a preset
state, best practice is to again rewrite the nvSRAM into the
desired state as a safeguard against events that might flip the
bit inadvertently (program bugs, incoming inspection routines,
and so on).
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Mode
Output High Z
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
I/O
STK11C68
Notes
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