STM32F100RET6B STMicroelectronics, STM32F100RET6B Datasheet - Page 78
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STM32F100RET6B
Manufacturer Part Number
STM32F100RET6B
Description
16/32-BITS MICROS
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet
1.STM32F100RCT6TR.pdf
(97 pages)
Specifications of STM32F100RET6B
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
24MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
51
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM32F100RET6B
Manufacturer:
NXP
Quantity:
11 430
Company:
Part Number:
STM32F100RET6B
Manufacturer:
STMicroelectronics
Quantity:
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Company:
Part Number:
STM32F100RET6BTR
Manufacturer:
STMicroelectronics
Quantity:
10 000
Electrical characteristics
78/97
SPI interface characteristics
Unless otherwise specified, the parameters given in
from tests performed under the ambient temperature, f
voltage conditions summarized in
Refer to
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 50.
1. Preliminary values.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
DuCy(SCK)
t
t
t
t
dis(SO)
t
w(SCKH)
t
w(SCKL)
su(NSS)
t
a(SO)
Symbol
1/t
t
t
t
t
t
t
h(NSS)
su(MI)
v(SO)
t
v(MO)
h(MO)
the data.
the data in Hi-Z
su(SI)
h(MI)
h(SO)
t
t
h(SI)
r(SCK)
f(SCK)
f
SCK
c(SCK)
(1)(2)
(1)
(1)(3)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Section 5.3.13: I/O current injection characteristics
(1)
(1)
(1)
SPI characteristics
SPI clock frequency
SPI clock rise and fall
time
SPI slave input clock
duty cycle
NSS setup time
NSS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time Slave mode, f
Data output disable time Slave mode
Data output valid time
Data output valid time
Data output hold time
Parameter
Doc ID 15081 Rev 5
Table
Master mode
Slave mode
Capacitive load: C = 30 pF
Slave mode
Slave mode
Slave mode
Master mode, f
presc = 4
Master mode
Slave mode
Master mode
Slave mode
Slave mode (after enable edge)
Master mode (after enable
edge)
Slave mode (after enable edge)
Master mode (after enable
edge)
9.
STM32F100xC, STM32F100xD, STM32F100xE
Conditions
PCLK
PCLK
Table 50
= 24 MHz
PCLKx
= 24 MHz,
for more details on the
frequency and V
are preliminary values derived
4t
2t
Min
PCLK
PCLK
30
15
50
5
5
5
4
2
2
0
3t
DD
Max
PCLK
12
10
25
70
60
12
5
8
supply
MHz
Unit
ns
ns
%