STM32F100RET6B STMicroelectronics, STM32F100RET6B Datasheet - Page 83
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STM32F100RET6B
Manufacturer Part Number
STM32F100RET6B
Description
16/32-BITS MICROS
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet
1.STM32F100RCT6TR.pdf
(97 pages)
Specifications of STM32F100RET6B
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
24MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
51
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM32F100RET6B
Manufacturer:
NXP
Quantity:
11 430
Company:
Part Number:
STM32F100RET6B
Manufacturer:
STMicroelectronics
Quantity:
10 000
Company:
Part Number:
STM32F100RET6BTR
Manufacturer:
STMicroelectronics
Quantity:
10 000
STM32F100xC, STM32F100xD, STM32F100xE
Any positive injection current within the limits specified for I
Section 5.3.13
Figure 33. ADC accuracy characteristics
Figure 34. Typical connection diagram using the ADC
1. Refer to
2. C
General PCB design guidelines
Power supply decoupling should be performed as shown in
depending on whether V
ceramic (good quality). They should be placed them as close as possible to the chip.
4095
4094
4093
pad capacitance (roughly 7 pF). A high C
this, f
7
6
5
4
3
2
1
parasitic
0
V
SSA
[1LSB
ADC
1
V AIN
Table 51
E
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
should be reduced.
IDEAL
O
2
does not affect the ADC accuracy.
=
V
R AIN (1)
4096
3
REF+
for the values of R
4
(or
C parasitic
V
5
REF+
1 LSB
4096
AINx
DDA
E
6
T
depending on package)]
IDEAL
is connected to V
Doc ID 15081 Rev 5
E
7
L
AIN
(2)
, R
V DD
parasitic
ADC
E
D
0.6 V
0.6 V
V T
V T
4093 4094 4095 4096
and C
(3)
value will downgrade conversion accuracy. To remedy
ADC
(1)
DDA
I L ±1 µA
.
E
G
or not. The 10 nF capacitors should be
V
DDA
Sample and hold ADC
converter
R ADC (1)
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
E
between the actual and the ideal transfer curves.
E
transition and the first ideal one.
E
transition and the last actual one.
E
between actual steps and the ideal one.
E
between any actual transition and the end point
correlation line.
T
O
G
D
L
=Total Unadjusted Error: maximum deviation
=Integral Linearity Error: maximum deviation
=Differential Linearity Error: maximum deviation
INJ(PIN)
=Offset Error: deviation between the first actual
=Gain Error: deviation between the last ideal
Figure 35
C ADC (1)
converter
Electrical characteristics
12-bit
STM32F10xxx
and ΣI
or
Figure
INJ(PIN)
ai14139d
36,
in
ai14395b
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