XRT59L921IB Exar Corporation, XRT59L921IB Datasheet
XRT59L921IB
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XRT59L921IB Summary of contents
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MARCH 2007 GENERAL DESCRIPTION The XRT59L921 is an optimized twenty-one channel, E1, line interface unit, fabricated using low power CMOS technology. The device contains twenty-one independent E1 channels primarily targeted towards the SDH multiplexers that accommodate TU12 Tributary ...
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... XRT59L921 TWENTY-ONE CHANNEL E1 LINE INTERFACE UNIT P N ART UMBER XRT59L921IB XRT59L921 ( IGURE THE Refer to pin list for pin names. OTE ORDERING INFORMATION P ACKAGE 316 Shrink Thin Ball Grid Array (21 21.0 mm, STBGA) ) BOTTOM VIEW REV. 1.2 PERATING EMPERATURE ANGE ° ° ...
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REV. 1.2.1 GENERAL DESCRIPTION................................................................................................. 1 F ..................................................................................................................................................... 1 EATURES A ............................................................................................................................................... 1 PPLICATIONS XRT59L921 ............................................................................................................................. 1 IGURE LOCK IAGRAM OF THE ORDERING INFORMATION .................................................................................................................... XRT59L921 ( IGURE THE ...
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XRT59L921 TWENTY-ONE CHANNEL E1 LINE INTERFACE UNIT F 17. I IGURE LLUSTRATION ON HOW TO INTERFACE 75W TO A UNBALANCED LINE F 18. I IGURE LLUSTRATION ON HOW TO INTERFACE 120W ) ........................................................................................................................................... BALANCED LINE ORDERING INFORMATION.............................................................................................29 ...
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REV. 1.2.1 PIN DESCRIPTIONS YMBOL YPE D8 RxPOS_0 O Receiver Positive Data Out – Channel_n: (n=0 to 20) C9 RxPOS_1 This output pin will pulse “High” whenever Channel_n, within the XRT59L921 has received a Positive ...
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XRT59L921 TWENTY-ONE CHANNEL E1 LINE INTERFACE UNIT PIN DESCRIPTIONS YMBOL YPE D7 LOS_0 O Receiver Loss of Signal Output Indicator – Channel_n: B8 LOS_1 This output pin toggles “High” if Channel_n, within the XRT59L921 has ...
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REV. 1.2.1 PIN DESCRIPTIONS YMBOL YPE C1 RRing_0 I Receiver Negative Bipolar Input – Channel_n: D2 RRing_1 The Receive Section of Channel_n uses this input pin, along with RTIP_n to receive the bipolar line signal ...
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XRT59L921 TWENTY-ONE CHANNEL E1 LINE INTERFACE UNIT PIN DESCRIPTIONS YMBOL YPE C4 TTIP_0 O Transmitter Positive Bipolar Output – Channel_n: D5 TTIP_1 Channel_n within the XRT59L921 will use this pin, along with TRing_n, to transmit ...
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REV. 1.2.1 PIN DESCRIPTIONS YMBOL YPE A2 TxClk_0 I Transmitter Clock Input – Channel_n: A4 TxClk_1 If the user operates Channel_n (within the XRT59L921) in the Clock mode, then the Transmit Section of the Channel_n ...
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XRT59L921 TWENTY-ONE CHANNEL E1 LINE INTERFACE UNIT PIN DESCRIPTIONS YMBOL YPE A3 TxPOS_0 I Transmitter - Positive Data Input – Channel_n: A5 TxPOS_1 The exact signal that should be applied to this input pin depends ...
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REV. 1.2.1 PIN DESCRIPTIONS YMBOL YPE D10 AVDD - Positive Supply - (+3.3V ± 5%). Receivers D12 AVDD U10 AVDD U12 AVDD L17 AVDD A1 DVDD - Positive Supply (+3.3V ± 5%). Digital Circuitry. A20 ...
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XRT59L921 TWENTY-ONE CHANNEL E1 LINE INTERFACE UNIT PIN DESCRIPTIONS YMBOL YPE H16 AGND - Ground Pins J9 J10 J11 J12 K9 K10 K11 K12 L9 L10 L11 L12 M9 M10 M11 M12 P5 P16 P17 ...
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REV. 1.2.1 PIN DESCRIPTIONS YMBOL YPE C2 TGND_0 - Digital Ground. Transmitter_n D3 TGND_1 F2 TGND_2 G3 TGND_3 J2 TGND_4 K3 TGND_5 M2 TGND_6 N3 TGND_7 R2 TGND_8 T3 TGND_9 V2 TGND_10 V19 TGND_11 T18 ...
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XRT59L921 TWENTY-ONE CHANNEL E1 LINE INTERFACE UNIT RECEIVER ELECTRICAL CHARACTERISTICS T =-40 to 85°C, V =3.3V±5%, unless otherwise specified Parameter M IN Receiver Loss of Signal: Threshold to Assert - Threshold to Clear - Time Delay 10 Hysteresis ...
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REV. 1.2 E1. ITU G.703 P T IGURE ULSE EMPLATE FOR – ...
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XRT59L921 TWENTY-ONE CHANNEL E1 LINE INTERFACE UNIT AC ELECTRICAL CHARACTERISTICS TA=-25°C, VDD=3.3V±5%, unless otherwise specified P ARAMETER TCLK Clock Period TCLK Duty Cycle Transmit Data Setup Time Transmit Data Hold Time Transmit Data Prop. Delay Time - RZ data Mode ...
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REV. 1.2.1 SYSTEM DESCRIPTION The XRT59L921 is a Twenty-One (21) channel E1 transceiver that provides an electrical interface for 2.048Mbps applications. Each of the twenty-one channels includes a receive circuit that converts an ITU-T G.703 compliant bipolar signal into a ...
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XRT59L921 TWENTY-ONE CHANNEL E1 LINE INTERFACE UNIT IGURE LLUSTRATION ON HOW THE PINS T TxPOS_n TxNEG_n TClk_n In general, if the XRT59L921 samples a “1” on the TxPOS_n input pin, then the Transmit Section of the device ...
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REV. 1.2 IGURE LLUSTRATION ON HOW THE C ( XRT59L921), GIVEN HANNEL WITHIN THE Bit Period DATA 1 TxPOS_n TxNEG_n TClk_n Figure 5, indicates that when the user is operating a channel in the Clockless Mode, then ...
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XRT59L921 TWENTY-ONE CHANNEL E1 LINE INTERFACE UNIT ITU-T G.703 P IGURE LLUSTRATION OF THE V = 100% 50% 0% Each channel (within the XRT59L921) will take each mark (which is provided to it via the Transmit Input ...
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REV. 1.2 IGURE LLUSTRATION OF HOW TO INTERFACE THE 75Ω PPLICATIONS TxPOS_n TxNEG_n TxClk_n IGURE LLUSTRATION OF HOW TO INTERFACE THE 120Ω PPLICATIONS XRT59L921 TxPOS_n TxPOS_n TxNEG_n TxNEG_n TxClk_n TxClk_n ...
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XRT59L921 TWENTY-ONE CHANNEL E1 LINE INTERFACE UNIT FOLLOWING RANSFORMERS ARE ART UMBER ENDOR PE-65835 Pulse TTI 7154-R Transpower Technologies, Inc. TG26-1205 HALO N : More transformers will be added to this list as they ...
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REV. 1.2.1 P.O. Box 5826 Redwood City, CA 94063 Tel: (650)568-5800 FAX: (650)568-6161 2.0 THE RECEIVE SECTION The Receive Sections of the XRT59L921 consists of the following blocks: • The Receive Equalizer block • The Peak Detector and Slicer block ...
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XRT59L921 TWENTY-ONE CHANNEL E1 LINE INTERFACE UNIT F 10 IGURE ECOMMENDED CHEMATIC FOR L 120Ω INE FOR PPLICATIONS RANSFORMER XRT59L921 RxPOS_n RxPOS_n RxNEG_n RxNEG_n LOS_n LOS_n Figure 9 Figure and indicate that the ...
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REV. 1.2.1 TRANSFORMER RECOMENDATION R T ECEIVE Primary Inductance Leakage Inductance 2.2 Interfacing the XRT59L921 Receive Section to the Line (Capacitive Coupling) Figure 11 and Figure 12 are recommended methods to Interface the the receive sections of the XRT59L921to the ...
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XRT59L921 TWENTY-ONE CHANNEL E1 LINE INTERFACE UNIT 2.3 The Receive Equalizer Bock After a given Channel (within the XRT59L921) has received the incoming line signal, via the RTIP_n and RRing_n input pins, the first block that this signal will pass ...
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REV. 1.2.1 indicator. In particular, the XRT59L921 will declare a LOS, between 10 and 255 UI (or E1 bit-periods) after the actual time the LOS condition occurred. Further, the XRT59L921 will clear the LOS indicator within 10 to 255 UI ...
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XRT59L921 TWENTY-ONE CHANNEL E1 LINE INTERFACE UNIT F 15 IGURE RANSMIT IMING IAGRAM TClk T TxPOS or TNEG TTIP/ TRing TxPOS or TNEG TTIP/ TRing F 16 IGURE ECEIVE IMING ...
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REV. 1.2.1 APPLICATION INFORMATION Figure 17 and Figure 18, provide example schematics on how to interface Channel 1 of the XRT59L921 to the line, under the following conditions. • Receiver is Transformer-coupled to a 75Ω unbalanced line. • Receiver is ...
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XRT59L921 TWENTY-ONE CHANNEL E1 LINE INTERFACE UNIT F 18. I IGURE LLUSTRATION ON HOW TO INTERFACE T - 120Ω RANSFORMER COUPLED TO A TxPOS_x TxNEG_x TxLineClk_x RxPOS_x RxNEG_x Loss Of Signal_x XRT59L921) HANNEL OF THE ) BALANCED ...
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... REV. 1.2.1 ORDERING INFORMATION P N RODUCT UMBER XRT59L921IB 316 Shrink Thin Ball Grid Array PACKAGE DIMENSIONS Note: The control dimension is in millimeter. SYMBOL TWENTY-ONE CHANNEL E1 LINE INTERFACE UNIT P ACKAGE (21 21.0 mm, STBGA) INCHES MILLIMETERS MIN MAX MIN 0.056 0.067 1.41 0.011 0.015 ...
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... Added pin V1 DGND in pin list. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...