SAB82525N-V21 Infineon Technologies, SAB82525N-V21 Datasheet - Page 45

• Manufacturer Part Number: SAB82525N-V21
• Manufacturer: Infineon Technologies

Specifications of SAB82525N-V21

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / RoHS Status: Compliant

If you use the write signal instead of the chip select signal in order to reset the DMA request
you gain some time. The extra circuit is just an AND gate. The first input of the AND gate is
connected to the DMA request line of the peripheral IC; the second input is connected to the
chip select line. The AND gate’s output is the DMA request signal for the 80(C)188.
Theoretically, the request line of an 80(C)188, for example, would still be active when the de-
termination is made and DMA cycles would be performed permanently. Therefore the decision
of the DMA request line is delayed; it is already made two clock cycles before the end of the
write cycle. If no wait-states are inserted the decision is made at the end of the T2 clock cycle.
Due to the fact that the write signal will be valid at the beginning of T2 there is only little time
left for resetting the DMA request line.
Semiconductor Group
CLOCKOUT
DRQ
RD
(Memory)
WR
(FIFO)
t
f
12.5
16
8 MHz
CLKOUT
DRHSYS max
MHz
MHz
= T2 - t
t
125 ns
80
62.5
CLCL
CVCTV
ns
ns
80(C)188
- t
INVCL
T1
t
56 ns
47
31
CVCTV
ns
ns
DRQ
PCS
T2
15 ns
15
15
t
INVCL
T3
ns
ns
T4
45
&
t
DRHSYS max
t
18
16.5
54 ns
CVCTV
t
DRHSYS
T1
ns
ns
T2
DRQTx
CS
t
INVCL
T3
HSCX
T4
ITS02699
SAB 82525
SAB 82526
SAF 82525
SAF 82526
ITD02698