DP83934CVUL-25/NOPB National Semiconductor, DP83934CVUL-25/NOPB Datasheet - Page 38

• Manufacturer Part Number: DP83934CVUL-25/NOPB
• Manufacturer: National Semiconductor

Specifications of DP83934CVUL-25/NOPB

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Compliant

15 –10
6 0 SONIC-T Registers
6 3 REGISTER DESCRIPTION
6 3 1 Command Register
(RA
This register (Figure 6-4) is used for issuing commands to the SONIC-T These commands are issued by setting the correspond-
ing bits for the function For all bits except for the RST bit the SONIC-T resets the bit after the command is completed With the
exception of RST writing a ‘‘0’’ to any bit has no effect Before any commands can be issued the RST bit must first be reset to
‘‘0’’ This means that if the RST bit is set two writes to the Command Register are required to issue a command to the
SONIC-T one to clear the RST bit and one to issue the command
This register also controls the general purpose 32-bit Watchdog Timer After the Watchdog Timer register has been loaded it
begins to decrement once the ST bit has been set to ‘‘1’’ An interrupt is issued when the count reaches zero if the Timer
Complete interrupt is enabled in the IMR
During hardware reset bits 7 4 and 2 are set to a ‘‘1’’ all others are cleared During software reset bits 9 8 1 and 0 are
cleared and bits 7 and 2 are set to a ‘‘1’’ all others are unaffected
Bit
9
8
7
6
5
4
r
k
e
5 0
15
read only r w
0
l
e
Must be 0
LCAM LOAD CAM
Setting this bit causes the SONIC-T to load the CAM with the descriptor that is pointed to by the CAM Descriptor
Pointer register
Note This bit must not be set during transmission (TXP is set) The SONIC-T will lock up if both bits are set simultaneously
RRRA READ RRA
Setting this bit causes the SONIC-T to read the next RRA descriptor pointed to by the Resource Read Pointer (RRP)
register Generally this bit is only set during initialization Setting this bit during normal operation can cause improper
receive operation
RST SOFTWARE RESET
Setting this bit resets all internal state machines The CRC generator is disabled and the Tally counters are halted
but not cleared The SONIC-T becomes operational when this bit is reset to ‘‘0’’ A hardware reset sets this bit to a
‘‘1’’ It must be reset to ‘‘0’’ before the SONIC-T becomes operational
Must be 0
ST START TIMER
Setting this bit enables the general-purpose watchdog timer to begin counting or to resume counting after it has
been halted This bit is reset when the timer is halted (i e STP is set) Setting this bit resets STP
STP STOP TIMER
Setting this bit halts the general-purpose watchdog timer and resets the ST bit The timer resumes when the ST bit is
set This bit powers up as a ‘‘1’’ Note Simultaneously setting bits ST and STP stops the timer
0h)
14
0
e
read write
13
0
12
0
11
0
(Continued)
LCAM
RRRA
RST
ST
STP
RXEN
RXDIS
TXP
HTX
Field
10
0
FIGURE 6-4 Command Register
LCAM RRRA RST
r w
9
r w
8
LOAD CAM
READ RRA
SOFTWARE RESET
START TIMER
STOP TIMER
RECEIVER ENABLE
RECEIVER DISABLE
TRANSMIT PACKET(S)
HALT TRANSMISSION
38
Description
r w
7
Meaning
r w
6
0
r w
ST
5
STP RXEN RXDIS TXP
r w
4
r w
3
r w
2
r w
1
HTX
0