DP83934CVUL-25/NOPB National Semiconductor, DP83934CVUL-25/NOPB Datasheet - Page 82

• Manufacturer Part Number: DP83934CVUL-25/NOPB
• Manufacturer: National Semiconductor

Specifications of DP83934CVUL-25/NOPB

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Compliant

9 0 AC and DC Specifications
MEMORY WRITE BMODE
Note 1 DS will only be asserted if the bus cycle has at least one wait state inserted
Note 2 For successive write operations MRW remains low
Note 3 DSACK0 1 must be synchronized to the bus clock (BSCK) during synchronous mode
Note 4 One idle clock cycle (Ti) will be inserted between the last write cycle and the following read cycle in RDA and TDA operation Note that the data bus will
become TRI-STATE from the rising edge of the clock after the idle cycle (see T52 for BSCK to data TRI-STATE timing)
Number
T9
T11a
T11c
T12a
T12c
T13a
T13b
T14
T15a
T18
T19
T20
T22
T30
T31
T36
T37a
T39
BSCK to Address Valid Hold Time
BSCK to AS Low
BSCK to ECS Low
BSCK to AS High
BSCK to ECS High
BSCK to DS High (Note 1)
BSCK to DS High (Note 1)
AS Low Width
AS High Width
Write Data Strobe Width (Note 1)
Address Hold Time from AS
Data Hold Time from AS
Address Valid to AS (Note 3)
DSACK0 1 Setup to BSCK (Note 3)
DSACK0 1 Hold from BSCK
BSCK to Memory Write Data Valid Hold
Time (Note 4)
BSCK to MRW (Write) Valid (Note 2)
Write Data Valid to Data Strobe Low
e
1 SYNCHRONOUS MODE (one wait-state shown)
Parameter
(Continued)
82
Min
44
45
40
18
20
34
3
9
5
9
3
20 MHz
Max
26
17
19
17
19
16
16
50
26
Min
34
35
30
14
16
21
3
6
4
8
3
25 MHz
Max
24
15
17
15
17
14
14
48
24
TL F 11719– 64
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns