DP83934CVUL-25/NOPB National Semiconductor, DP83934CVUL-25/NOPB Datasheet - Page 81

• Manufacturer Part Number: DP83934CVUL-25/NOPB
• Manufacturer: National Semiconductor

Specifications of DP83934CVUL-25/NOPB

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Compliant

9 0 AC and DC Specifications
MEMORY READ BMODE
Note 1 For successive read operations MWR remains low
Note 2 This setup time assures that the SONIC-T terminates the memory cycle on the next bus clock (BSCK) RDYi does not need to be synchronized to the bus
clock though since it is an asynchronous input in this case RDYi is sampled during the falling edge of BSCK If the SONIC-T samples RDYi low during the T1
cycle the SONIC-T will finish the current access in a total of two bus clocks instead of three which would be the case if RDYi had been sampled low during
T2 (wait) (This is assuming that programmable wait states are set to 0 )
Number
T9
T11
T11b
T11d
T12
T12b
T12d
T15
T16
T17
T23
T24
T28
T32a
T33a
BSCK to Address Valid Hold Time
BSCK to ADS Low
BSCK to ECS Low
BSCK to DS Low
BSCK to ADS High
BSCK to ECS High
BSCK to DS High
ADS High Width
Read Data Strobe High Width
Read Data Strobe Low Width
Read Data Setup Time to BSCK
Read Data Hold Time from BSCK
BSCK to MWR (Read) Valid (Note 1)
RDYi Asynchronous Setup Time to BSCK (Note 2)
RDYi Asynchronous Hold Time to BSCK
e
0 ASYNCHRONOUS MODE
Parameter
(Continued)
81
Min
45
45
40
3
6
5
5
5
20 MHz
Max
26
26
19
17
24
29
17
26
Min
35
35
30
3
5
5
4
5
25 MHz
Max
24
24
17
15
22
27
15
24
TL F 11719 – 63
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns