TRCV0110G LSI, TRCV0110G Datasheet
TRCV0110G
Specifications of TRCV0110G
Related parts for TRCV0110G
TRCV0110G Summary of contents
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... Gbits/s high-speed communications systems. Additional features include an auxiliary clock output and a reference clock input that can be either divided divided by 64. The TRCV0110G can be operated within the standard OC192/STM64 data rate of 9.9532 GHz and the FEC rate of 10.7092 Gbits/s. ...
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Clock Recovery, 1:16 Data Demultiplexer Contents Features .................................................................................................................................................................... 1 Applications ............................................................................................................................................................... 1 Description.................................................................................................................................................................1 Block Diagram......................................................................................................................................................... 3 Ball Information..........................................................................................................................................................4 Package Diagram ................................................................................................................................................... 4 Ball Assignments ....................................................................................................................................................5 Ball Description ....................................................................................................................................................... 7 Functional Overview ................................................................................................................................................11 FEC Rate Support ...................................................................................................................................................11 High-Speed Data Inputs ..........................................................................................................................................11 ...
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... Note: Diagram is representative of device functionality and conceptual signal flow. Internal implementation details may be different than shown. Agere Systems Inc. Clock Recovery, 1:16 Data Demultiplexer RECOVERED DATA 0 1 RECOVERED CLOCK SAMPLER CIRCUIT DIVIDE BY 16 CHARGE VCO PUMP LFP LFN Figure 1. TRCV0110G Block Diagram MUTEDMXN D0P D0N D1P D1N D15P D15N MUTE622N 0 CK622P CK622N 1 FREQCKO MUTECKO MUTECKON DIVIDE BY 1 ...
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Clock Recovery, 1:16 Data Demultiplexer Ball Information Package Diagram Figure 2. Ball Diagram of 177-Ball CBGA/FSBGA1 ...
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June 7, 2002 Ball Information (continued) Ball Assignments Table 1. Ball Assignments for 177-Ball CBGA/FSBGA1 by Ball Number Order Ball Signal Name Ball A1 GND CCD A3 FECN C3 A4 REFFREQ C4 A5 FREQCKO C5 A6 ...
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Clock Recovery, 1:16 Data Demultiplexer Ball Information (continued) Ball Assignments (continued) Table 1. Ball Assignments for 177-Ball CBGA/FSBGA1 by Ball Number Order (continued) Ball Signal Name Ball J1 D3P K8 J2 GND K9 J3 GND K10 J4 — K11 J5 ...
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... Ball Information (continued) Ball Description Note: In Table 2, when operating the TRCV0110G device at the OC-192/STM-64 rate, 10 Gbits/s should be interpreted as 9.95328 Gbits/s. When operating the TRCV0110G device at the RS FEC OC-192/STM-64 rate, 10 Gbits/s should be interpreted as 10.709 Gbits/s. When operating the TRCV0110G device at the Ethernet rate, 10 Gbits/s should be interpreted as 10.3125 Gbits/s. ...
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... Ball Description (continued) Note: In Table 3, when operating the TRCV0110G device at the OC-192/STM-64 rate, 155 Mbits/s should be interpreted as 155.52 Mbits/s. When operating the TRCV0110G device at the RS FEC OC-192/STM-64 rate, 155 Mbits/s should be interpreted as 167.33 Mbits/s. Table 3. Ball Descriptions—622.08 Mbits/s and Related Signals * † ...
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June 7, 2002 Ball Information (continued) Ball Description (continued) Table 3. Ball Descriptions—622.08 Mbits/s and Related Signals (continued) * Ball Symbol Type B1 MUTEDMXN B5 MUTE622N A5 FREQCKO B4 MUTECKON A4 REFFREQ P12 REFCLKP N12 REFCLKN P11 CK622P N11 CK622N ...
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Clock Recovery, 1:16 Data Demultiplexer Ball Information (continued) Ball Description (continued) Table 4. Ball Descriptions—Reset * Ball Symbol B2 RESETN * Differential pins are indicated by the P and N suffixes. For nondifferential pins the end of the ...
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... High-Speed Data Inputs Limiting Amplifier Operation The TRCV0110G data input circuit contains a limiting amplifier that has approximately voltage gain. As shown in Figure 3, the DATAP/N inputs should be ac-coupled. These ac-coupling capacitors are typically included inside the optical receiver package. For applications requiring ac-coupling external to the O/E device, insert low ESR 0 ...
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... The clock and data recovery (CDR) circuit uses a PLL to extract the clock and retime the 10 Gbits/s data. The TRCV0110G uses an external loop filter that is described below in Figure 5. A 622 MHz clock derived from the recovered clock is available as an output at CK622P/N. A 622 MHz or 155 MHz clock derived from the recovered clock is available as an auxiliary output at CKOP/N ...
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June 7, 2002 CDR Input Jitter Tolerance 100 10 1 0.1 0.01 Agere Systems Inc. Clock Recovery, 1:16 Data Demultiplexer MODULATION FREQUENCY (kHz) Figure 6. Receive Jitter Tolerance Mask 0365.a(F) 13 ...
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... Lock Detect By the behavior of the LCKLOSSN pin, the user can identify three possible loss-of-lock scenarios. If desired, the user can configure the TRCV0110G to lock directly to the REFCLK input during any of these conditions. See the TRCV0110G LCKLOSSN Application Note. The TRCV0110G contains a frequency detect circuit that compares the frequency of the internal VCO to the REFCLK. LCKLOSSN transitions low if the frequencies differ by approximately ± ...
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June 7, 2002 Demultiplexer Operation The serial 10 Gbits/s data is clocked into a 1:16 demultiplexer by the recovered 10 GHz clock. The demultiplexed parallel data is retimed with a 622 MHz clock that is derived from the recovered clock. ...
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... JEDEC's JESD22-A114 (HBM) and JESD22-C101 (CDM) standards. Table 7. Handling Precautions Device TRCV0110G Note: All LVDS, CMOS, and analog pins (except high-speed and ACM) have an ESD HBM threshold of 2,000 V. Recommended Operating Conditions Recommended operating conditions apply unless otherwise specified. ...
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June 7, 2002 Electrical Characteristics LVDS, CMOS, and CML Input and Output Pins Table 9. LVDS dc Output Pin Characteristics Parameter Applicable Output Voltage High D[15:0]P/N, CKOP/N Output Voltage Low CK622P/N Output Differential Volt- † age Output Offset Voltage Differential ...
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Clock Recovery, 1:16 Data Demultiplexer Electrical Characteristics LVDS, CMOS, and CML Input and Output Pins Table 11. CMOS Input Pin Characteristics Parameter Applicable Input Voltage High RESETN, Input Voltage Low ENLBDN, Input Current High Leakage REFFREQ, Input Current Low Leakage ...
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June 7, 2002 Timing Characteristics Note that all timing diagrams involving differential signals represent the positive signal as a solid line and the neg- ative signal as a dashed line. This is especially important when referencing the rising or falling ...
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... Clock Recovery, 1:16 Data Demultiplexer Timing Characteristics (continued) Output Timing The following diagram and specs are from the 10 Gbit MSA document. You will notice the TRCV0110G device specs compared to the 300-pin 10 Gbit MSA spec's in the data table. RxPOCLKN RxD Table 15. Output Data/Clock Phase ...
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June 7, 2002 Timing Characteristics (continued) Reference Frequency (REFCLKP/N, REFFREQ) (Standard SONET Rate) The device requires a 155.52 MHz or 622.08 MHz differential LVDS reference clock input to aid in frequency acquisition and loss-of-lock detection. Table 16. OC-192 Reference Clock ...
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Clock Recovery, 1:16 Data Demultiplexer Packaging Characteristics CBGA (Ceramic Ball Grid Array) Package Information The substrate is 99.6% alumina (Al2O3) material. The standoff height is accomplished by using 0.013 in. diameter copper silver (CuAg) balls, which are attached using a ...
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June 7, 2002 Packaging Characteristics CBGA Assembly Information Note: Each assembly process will have its own idiosyncrasies, due to product design, materials differences, and equipment variations. Assembly information provided here is a beginning point from which the assembly process engineer ...
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Clock Recovery, 1:16 Data Demultiplexer Packaging Characteristics CBGA Suggested Underfill Process 1. Assemble PWB. Reflow solder and clean per standard processes. 2. Refer to manufacturer’s data sheet for material handling, application, and cure. 3. Thaw out the Hysol 4549 material ...
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June 7, 2002 Packaging Characteristics Package Diagram—177-Ball CBGA (Bottom View) Dimensions are in millimeters. Tolerance is ±0.076 mm unless otherwise noted. A1 BALL IDENTIFIER ZONE 1.885 0.3734 0.330 0.051 TYP DIA A1 BALL CORNER Agere Systems Inc. Clock Recovery, 1:16 ...
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... Packaging Characteristics FSBGA1 Package Information The package used for the plastic version of the TRCV0110G device is generically a plastic ball grid array (PBGA). The Agere name for this specific type of package is a fully singulated ball grid array, 1.0 mm ball pitch (FSBGA1). The substrate is organic BT (Bismalemide Triazene) material, with a plastic over mold. The standoff height is accomplished using 0 ...
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June 7, 2002 Packaging Characteristics Table 20. JEDEC Profile Belt speed = 28 in./min. Zone 1 Upper Lower 2 Upper Lower 3 Upper Lower 4 Upper Lower 5 Upper Lower 6 Upper Lower 7 Upper Lower A representative sample of ...
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Clock Recovery, 1:16 Data Demultiplexer Packaging Characteristics Package Diagram—177-Ball FSBGA1 (Bottom View) Dimensions are in millimeters. Tolerance is ±0.10 mm unless otherwise noted. A1 BALL IDENTIFIER ZONE 1.56 0.18 0.36 0.08 0.63 0.10 TYP DIA A1 BALL CORNER 28 (continued) ...
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... June 7, 2002 Ordering Information Device Code TRCV0110G TRCV0110G-3-XE Agere Systems Inc. Clock Recovery, 1:16 Data Demultiplexer Package Temperature (T 177-ball CBGA 0—85 177-ball FSBGA1 0—85 ) Comcode C (Ordering Number) 108698499 7000199050 29 ...
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Telcordia Technologies is a trademark of Telcordia Technologies Inc. National and National Semiconductor are registered trademarks of National Semiconductor Corporation. IEEE is a registered trademark of The institute of Electrical and Electronics Engineers, Inc. For additional information, contact your Agere ...