SCN68681E1A44 NXP Semiconductors, SCN68681E1A44 Datasheet - Page 15

• Manufacturer Part Number: SCN68681E1A44
• Manufacturer: NXP Semiconductors

Specifications of SCN68681E1A44

• Transmitter And Receiver Fifo Counter: No
• Operating Supply Voltage (typ): 5V
• Package Type: PLCC
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Surface Mount
• Pin Count: 44
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Number Of Channels: 2
• Lead Free Status / RoHS Status: Not Compliant

external 1X clock. This will usually require a HIGH time of one X1
Philips Semiconductors
CRA[1] – Disable Channel A Receiver
This command terminates operation of the receiver immediately – a
character being received will be lost. The command has no effect on
the receiver status bits or any other control registers. If the special
multidrop mode is programmed, the receiver operates even if it is
disabled. See Operation section.
CRA[0] – Enable Channel A Receiver
Enables operation of the Channel A receiver. If not in the special
wake up mode, this also forces the receiver into the search for
start-bit state.
CRB – Channel B Command Register
CRB is a register used to supply commands to Channel B. Multiple
commands can be specified in a single write to CRB as long as the
commands are non-conflicting, e.g., the ‘enable transmitter’ and
‘reset transmitter’ commands cannot be specified in a single
command word.
The bit definitions for this register are identical to the bit definitions
for CRA, except that all control actions apply to the Channel B
receiver and transmitter and the corresponding inputs and outputs.,
SRA – Channel A Status Register
SRA[7] – Channel A Received Break
This bit indicates that an all zero character of the programmed
length has been received without a stop bit. Only a single FIFO
position is occupied when a break is received further entries to the
FIFO are inhibited until the RxDA line to the marking state for at
least one-half a bit time two successive edges of the internal or
clock period or 3 X1 edges since the clock of the controller is
not synchronous to the X1 clock.
When this bit is set, the Channel A ‘change in break’ bit in the ISR
(ISR[2]) is set. ISR[2] is also set when the end of the break
condition, as defined above, is detected.
The break detect circuitry can detect breaks that originate in the
middle of a received character. However, if a break begins in the
middle of a character, it must persist until at least the end of the next
character time in order for it to be detected.
SRA[6] – Channel A Framing Error
This bit, when set, indicates that a stop bit was not detected when
the corresponding data character in the FIFO was received. The
stop bit check is made in the middle of the first stop bit position.
SRA[5] – Channel A Parity Error
This bit is set when the ‘with parity’ or ‘force parity’ mode is
programmed and the corresponding character in the FIFO was
received with incorrect parity.
In the special multidrop mode the parity error bit stores the receive
A/D bit.
SRA[4] – Channel A Overrun Error
This bit, when set, indicates that one or more characters in the
received data stream have been lost. It is set upon receipt of a new
character when the FIFO is full and a character is already in the
receive shift register waiting for an empty FIFO position. When this
occurs, the character in the receive shift register (and its break
detect, parity error and framing error status, if any) is lost.
This bit is cleared by a ‘reset error status’ command.
SRA[3] – Channel A Transmitter Empty (TxEMTA)
This bit will be set when the transmitter underruns, i.e., both the
TxEMT and TxRDY bits are set. This bit and TxRDY are set when
the transmitter is first enabled and at any time it is re-enabled after
2004 Mar 02
Dual asynchronous receiver/transmitter (DUART)
15
either (a) reset, or (b) the transmitter has assumed the disabled
state. It is always set after transmission of the last stop bit of a
character if no character is in the THR awaiting transmission.
It is reset when the THR is loaded by the CPU, a pending
transmitter disable is executed, the transmitter is reset, or the
transmitter is disabled while in the underrun condition.
SRA[2] – Channel A Transmitter Ready (TxRDYA)
This bit, when set, indicates that the THR is empty and ready to be
loaded with a character. This bit is cleared when the THR is loaded
by the CPU and is set when the character is transferred to the transmit
shift register. TxRDY is reset when the transmitter is disabled and is
set when the transmitter is first enabled, viz., characters loaded into
the THR while the transmitter is disabled will not be transmitted.
SRA[1] – Channel A FIFO Full (FFULLA)
This bit is set when a character is transferred from the receive shift
register to the receive FIFO and the transfer causes the FIFO to
become full, i.e., all three FIFO positions are occupied. It is reset
when the CPU reads the RHR. If a character is waiting in the
receive shift register because the FIFO is full, FFULL will not be
reset when the CPU reads the RHR.
SRA[0] – Channel A Receiver Ready (RxRDYA)
This bit indicates that a character has been received and is waiting
in the FIFO to be read by the CPU. It is set when the character is
transferred from the receive shift to the FIFO and reset when the
CPU reads the RHR, if after this read there are not more characters
still in the FIFO.
SRB – Channel B Status Register
The bit definitions for this register are identical to the bit definitions
for SRA, except that all status applies to the Channel B receiver and
transmitter and the corresponding inputs and outputs.
OPCR – Output Port Configuration Register
OPCR[7] – OP7 Output Select
This bit programs the OP7 output to provide one of the following:
0: The complement of OPR[7].
1: The Channel B transmitter interrupt output which is the comple-
OPCR[6] – OP6 Output Select
This bit programs the OP6 output to provide one of the following:
0: The complement of OPR[6].
1: The Channel A transmitter interrupt output which is the comple-
OPCR[5] – OP5 Output Select
This bit programs the OP5 output to provide one of the following:
0: The complement of OPR[5].
1: The Channel B transmitter interrupt output which is the comple-
OPCR[4] – OP4 Output Select
This field programs the OP4 output to provide one of the following:
0: The complement of OPR[4].
1: The Channel A receiver interrupt output which is the complement
output. Note that this output is not masked by the contents of the
ment of TxRDYB. When in this mode OP7 acts as an open-
drain output. Note that this output is not masked by the contents
of the IMR.
ment of TxRDYA. When in this mode OP6 acts as an open-
drain output. Note that this output is not masked by the contents
of the IMR.
ment of ISR[5]. When in this mode OP5 acts as an open-drain
IMR.
of ISR[1]. When in this mode OP4 acts as an open-drain output.
Note that this output is not masked by the contents of the IMR.
SCN68681
Product data