SCN2681AE1A44 NXP Semiconductors, SCN2681AE1A44 Datasheet - Page 14

• Manufacturer Part Number: SCN2681AE1A44
• Manufacturer: NXP Semiconductors

Specifications of SCN2681AE1A44

• Transmitter And Receiver Fifo Counter: No
• Operating Supply Voltage (typ): 5V
• Package Type: PLCC
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Surface Mount
• Pin Count: 44
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Number Of Channels: 2
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
MR1B – Channel B Mode Register 1
MR1B is accessed when the Channel B MR pointer points to MR1.
The pointer is set to MR1 by RESET or by a ‘set pointer’ command
applied via CRB. After reading or writing MR1B, the pointer will point
to MR2B.
MR2B – Channel B Mode Register 2
MR2B is accessed when the Channel B MR pointer points to MR2,
which occurs after any access to MR1B. Accesses to MR2B do not
change the pointer.
The bit definitions for mode registers 1 and 2 are identical to the bit
definitions for MRA and MR2A except that all control actions apply
to the Channel B receiver and transmitter and the corresponding
inputs and outputs.
CSRA – Channel A Clock Select Register
CSRA[7:4] – Channel A Receiver Clock Select
This field selects the baud rate clock for the Channel A receiver as
follows:
(See also Table 5)
The receiver clock is always a 16X clock except for CSRA[7] = 1111.
CSRA[3:0] – Channel A Transmitter Clock Select
This field selects the baud rate clock for the Channel A transmitter.
The field definition is as per CSR[7:4] except as follows:
The transmitter clock is always a 16X clock except for
CSR[3:0] = 1111.
2004 Mar 18
Dual asynchronous receiver/transmitter (DUART)
CSRA[7:4]
CSRA[3:0]
0000
0001
0010
0011
0100
0101
0110
1000
1001
1010
1011
1100
1101
0111
1110
1111
1110
1111
ACR[7] = 0
ACR[7] = 0
IP4–16X
IP3–16X
IP4–1X
IP3–1X
134.5
1,200
1,050
2,400
4,800
7,200
9,600
Timer
38.4k
110
200
300
600
50
Baud Rate
ACR[7] = 1
Baud Rate
ACR[7] = 1
IP4–16X
IP3–16X
IP4–1X
IP3–1X
134.5
1,200
2,000
2,400
4,800
1,800
9,600
19.2k
Timer
110
150
300
600
75
14
CSRB – Channel B Clock Select Register
CSRB[7:4] – Channel B Receiver Clock Select
This field selects the baud rate clock for the Channel B receiver. The
field definition is as per CSRA[7:4] except as follows:
The receiver clock is always a 16X clock except for CSRB[7:4] = 1111.
CSRB[3:0] – Channel B Transmitter Clock Select
This field selects the baud rate clock for the Channel B transmitter.
The field definition is as per CSRA[7:4] except as follows:
The transmitter clock is always a 16X clock except for
CSRB[3:0] = 1111.
CRA – Channel A Command Register
CRA is a register used to supply commands to Channel A. Multiple
commands can be specified in a single write to CRA as long as the
commands are non-conflicting, e.g., the ‘enable transmitter’ and
‘reset transmitter’ commands cannot be specified in a single
command word.
CRA[7] – Not Used
Should be set to zero for upward compatibility with newer parts.
CRA[6:4] – Channel A Miscellaneous Command
The encoded value of this field may be used to specify a single
command as follows:
CRA[6:4] – COMMAND
000
001
010
011
100
101
CSRB[7:4]
CSRB[3:0]
No command.
Reset MR pointer. Causes the Channel A MR pointer to point
to MR1.
Reset receiver. Resets the Channel A receiver as if a
hardware reset had been applied. The receiver is disabled
and the FIFO is flushed.
Reset transmitter. Resets the Channel A transmitter as if a
hardware reset had been applied.
Reset error status. Clears the Channel A Received Break,
Parity Error, and Overrun Error bits in the status register
(SRA[7:4]). Used in character mode to clear OE status
(although RB, PE and FE bits will also be cleared) and in
block mode to clear all error status after a block of data has
been received.
Reset Channel A break change interrupt. Causes the
Channel A break detect change bit in the interrupt status
register (ISR[2]) to be cleared to zero.
1110
1111
1110
1111
IP5–16X
IP5–1X
ACR[7] = 0
ACR[7] = 0
IP6–16X
IP6–1X
SCN2681
IP5–16X
IP5–1X
ACR[7] = 1
ACR[7] = 1
Baud Rate
Baud Rate
IP6–16X
IP6–1X
Product data