SC28C94A1N NXP Semiconductors, SC28C94A1N Datasheet - Page 10

• Manufacturer Part Number: SC28C94A1N
• Manufacturer: NXP Semiconductors

Specifications of SC28C94A1N

• Transmitter And Receiver Fifo Counter: No
• Operating Supply Voltage (typ): 5V
• Package Type: PDIP
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Through Hole
• Pin Count: 48
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
WAKE-UP MODE (MULTI-DROP OR 9-BIT)
In addition to the normal transmitter and receiver operation described
above, the QUART incorporates a special mode which provides
automatic “wake up” of a receiver through address frame (or character)
recognition for multi-processor or multi-station communications. This
mode is selected by programming MR1[4:3] to ‘11’.
In this mode of operation a ‘master’ station transmits an address
character to the several ‘slave’ stations on the line. The address
character is identified by setting its parity bit to 1. The slave stations
will usually have their receivers partially enabled as a result of
setting MR1[4:3] to 11. When the receiver sees a one in the parity
position, it considers it an address bit and loads that character to the
RxFIFO and set the RxRDY bit in the status register. The user
would usually set the receiver interrupt to occur on RxRDY as well.
(All characters whose parity bits are set to 0 will be ignored). The
local processor at the slave station will read the ‘address’ character
just received. The local processor will test for an address match for
this station and if match occurs it will enable the local receiver and
receive the following data characters. The master will normally
follow an address character(s) with data characters. Since the data
characters transmitted by the master will have their parity bits set to
zero, stations other than the addressed one(s) will ignore the data.
NOTE: The time between address and data fields must be
enough for the local processor to test the address character
and enable the receiver. At bit times approaching 10 s this may
begin to be a point of concern.
The parity (Address/Data) bit should not be changed until the last stop
bit of an address has been sent. Similarly the A/D bit should not be
changed to address until the last stop bit has been sent. Either of
these conditions will be indicated by an active TxEMT bit in the SR.
The parity bit is not part of the TxFIFO. It is in the transmitter state
machine. However, it could be controlled in the FIFO if 5, 6 or 7 bit
data was transmitted by using a 6, 7 or 8 bit character. The most
significant bit would then be in the ‘parity’ position and represent the
A/D bit. The design of the UART is based, however, on the A/D bit
being controlled from the MR register.
Parity should be changed immediately before the data bytes
will be loaded to the transmitter.
A transmitted character consists of a start bit, the programmed
number of data and stop bits and an “address/data” bit. The parity
bit is used as the address or data indicator. The polarity of the A/D
bit is selected by setting MR1[2] to zero or one; zero indicates that
the current byte is data, while one indicates that the current byte is
addressed. The desired polarity of the A/D bit (parity) should be
programmed before the TxFIFO is loaded.
The receiver should be enabled before the beginning of the first data
bit. The time required is dependent on the interrupt latency of the
slave receivers. The transmitter is able to start data immediately
after the address byte has been sent.
While in this mode, the receiver continuously looks at the received
data stream, whether it is enabled or disabled. If disabled, it sets the
RxRDY status bit and loads the character in the RxFIFO if the
received A/D bit is a one, but discards the received character if the
received A/D bit is a zero. If enabled, all received characters are
then transferred to the CPU via the RxFIFO. In either case, the data
bits are loaded in the data FIFO while the A/D bit is loaded in the
status FIFO position normally used for parity error (SR[5]). Framing
error, overrun error, and break detect operate normally whether or
not the receiver is enabled.
2006 Aug 09
Quad universal asynchronous receiver/transmitter (QUART)
10
INPUT OUTPUT (I/O) PINS
There are 16 multi-use pins; four for each UART. These pins are
accessed and controlled via the Input Port Register (IPR), I/O Port
Control Register (I/OPCR), Input Port Change Register (IPCR), and
Output Port Register (OPR). They may be individually programmed
to be inputs or outputs. See Table 5.
I/O0x and I/O1x pins have change of state detectors. The change of
state detectors sample the input ports every 26.04 s (with the X1
clock at 3.686400MHz) and set the change bit in the IPCR if the pin
has changed since it was last read. Whether the pins are
programmed as inputs or outputs the change detectors still operate
and report changes accordingly. See the register descriptions of the
I/O ports for the detailed use of these features.
A read of the IPCR resets the I/O COS (Change Of State) detectors.
Interrupt Priority System
The interrupt control for the QUART has been designed to provide
very low interrupt service overhead for the controlling processor
while maintaining a high degree of flexibility in setting the
importance of interrupts generated in different functional blocks of
the device.
This is accomplished by allowing each function of the QUART (18
total) which may cause an interrupt to generate a variable numeric
code which contains the identity of the source, channel number and
severity level. This code is compared (at the X1 clock rate or the X1
clock rate divided by 2) to an interrupt threshold. When the
interrupting source generates a code that is numerically greater than
the interrupt threshold the IRQN is asserted
This is referred to as the bidding process. The winning bid contains,
in different fields, all the characteristics of the winning bidder. This
data may be used in several ways to steer the controlling processor
to the proper type and amount of service required (usually the
amount of service refers to the number of bytes written to the
transmitter or read from the receiver). Access to the winning bidder
is provided via the CIR (Current Interrupt Register), interrupt
vectors, modified interrupt vectors and Global registers.
NOTE: IRQN is essentially a level output. It will go active on an
interrupt condition and stays active until all interrupting sources are
serviced.
IRQN is designed to be an open drain active low level output. It will
go low under the control of the arbitration system and remain low
until the arbitration has determined that no more sources require
service.
When only one Rx or Tx is interrupting, it is possible to see the
IRQN assert more than once if, during an access to the FIFO, the
CEN input is inactive for more than two cycles of the X1 clock or X1
divide by 2 if that feature is enabled.
IACKN may be thought of as a special read input. Driving IACKN
low will update the CIR and then read the Interrupt Vector Register
or the Interrupt Vector Register modified by the CIR.
SC28C94
Product data sheet