SC28C94A1N NXP Semiconductors, SC28C94A1N Datasheet - Page 7

• Manufacturer Part Number: SC28C94A1N
• Manufacturer: NXP Semiconductors

Specifications of SC28C94A1N

• Transmitter And Receiver Fifo Counter: No
• Operating Supply Voltage (typ): 5V
• Package Type: PDIP
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Through Hole
• Pin Count: 48
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
FUNCTIONAL BLOCKS
The QUART is composed of four Philips Semiconductors
industry–standard UARTs, each having a separate transmit and
receive channel.
The Basic UART cells in the QUART are configured with 8-byte
Receive FIFOs and 8-byte Transmit FIFOs. Hardware supports
interrupt priority arbitration based on the number of bytes available
in the transmit and receive FIFOs, counter/timers, change of state
detectors, break detect or receiver error. Attempts to push a full
FIFO or pop an empty FIFO do not affect the count.
Baud Rate Generator
The baud rate generator used in the QUART is the same as that
used in other Philips Semiconductors industry standard UARTs. It
provides 18 basic Baud rates from 50 baud to 38,400 baud. It has
been enhanced to provide to provide other baud rates up to 230,400
baud based on a 3.6364MHz clock; with an 8.0MHz clock rates to
500K baud. Other rates are available by setting the BRG rate to high
at address 2D hex or setting Test 1 on at address 39 hex. See
Table 6. These two modes are controlled by writing 00 or 01 to the
addresses above. They are both set to 00 on reset. External Rx and
Tx clocks yield rates to 1MHz in the 16X mode.
BLOCK DIAGRAM
As shown in the block diagram, the QUART consists of: data bus
buffer, interrupt control, operation control, timing, and four receiver
and transmitter channels. The four channels are divided into two
different blocks, each block independent of the other.
Channel Blocks
There are two blocks (Block Diagram), each containing two sets of
receiver/transmitters. In the following discussion, the description
applies to Block A which contains channels a and b. However, the
same information applies to all channel blocks.
Data Bus Buffer
The data bus buffer provides the interface between the external and
internal data buses. It is controlled by the operation control block to
allow read and write operations to take place between the controlling
CPU and the QUART.
Operation Control
The operation control logic receives operation commands from the
CPU and generates appropriate signals to internal sections to
control device operation. It contains address decoding and read and
write circuits to permit communications with the microprocessor via
the data bus buffer. The functions performed by the CPU read and
write operations are shown in Table 1.
Mode registers (MR) 0, 1 and 2 are accessed via an address
counter. This counter is set to one (1) by reset or a command 1x to
the Command Register for compatibility with other Philips
Semiconductors software. It is set to 0 via a command Bx to the
Command Register (CR). The address counter is incremented with
each access to the MR until it reaches 2 at which time it remains at
2. All subsequent accesses to the MR will be to MR2 until the MR
counter is changed by a reset or an MR counter command.
The Mode Registers control the basic configuration of the UART
channels. There is one for each UART. (Transmitter/receiver pair)
Timing Circuits
The timing block consists of a crystal oscillator, a baud rate
generator, power up/down logic and a divide by 2 selector. Closely
associated with the timing block are two 16-bit counter/timers; one
for each DUART.
2006 Aug 09
Quad universal asynchronous receiver/transmitter (QUART)
7
Oscillator
The crystal oscillator operates directly from a 3.6864MHz crystal
connected across the X1/CLK and X2 inputs with a minimum of
external components. If an external clock of the appropriate
frequency is available, it may be connected to X1/CLK. If an external
clock is used instead of a crystal, X1 must be driven and X2 left
floating as shown in Figure 14. The clock serves as the basic timing
reference for the baud rate generator (BRG), the counter/timer, and
other internal circuits. A clock frequency, within the limits specified in
the electrical specifications, must be supplied even if the internal
BRG is not used.
The X1 pin always supplies the clock for the baud rate generator.
The X1 pin also has a feature such that it may be divided by 2. The
divide by two mode must always be used whenever the X1 pin is
above 4MHz. The baud rate generator supplies the standard rates
when X1 is at 3.6864MHz. In the divide by 2 mode, all circuits
receive the divide by two clock except baud rate generator and I/O
pin change-of-state detectors. The use of a 7.3738MHz X1 clock
doubles standard baud rates.
Baud Rate Generator
The baud rate generator operates from the oscillator or external
clock input and is capable of generating 18 commonly used data
communications baud rates ranging from 50 to 38.4K baud. The
eighteen BRG rates are grouped in two groups. Eight of the 18 are
common to each group. The group selection is controlled by ACR[7].
See the Baud Rate Table 6. The clock outputs from the BRG are at
16X the actual baud rate. The counter/timer can be used as a timer
to produce a 16X clock for any other baud rate by counting down the
crystal clock or an external clock. The clock selectors allow the
independent selection, by the receiver and transmitter, of any of
these baud rates or an external timing signal.
Counter/Timer
The counter timer is a 16-bit programmable divider that operates in
one of three modes: counter, timer, time out. In the timer mode it
generates a square wave. In the counter mode it generates a time
delay. In the time out mode it monitors the time between received
characters. The C/T uses the numbers loaded into the
Counter/Timer Lower Register (CTLR) and the Counter/Timer Upper
Register (CTUR) as its divisor.
There are two counter/timers in the QUART; one for each block.
The counter/timer clock source and mode of operation (counter or
timer) is selected by the Auxiliary Control Register bits 6 to 4
(ACR[6:4]). The output of the counter/timer may be used for a baud
rate and/or may be output to the I/O pins for some external function
that may be totally unrelated to data transmission. The
counter/timer also sets the counter/timer ready bit in the Interrupt
Status Register (ISR) when its output transitions from 1 to 0.
A register read address (see Table 1) is reserved to issue a start
counter/timer command and a second register read address is
reserved to issue a stop command. The value of D(7:0) is ignored.
The START command always loads the contents of CTUR, CTLR to
the counting registers. The STOP command always resets the
ISR(3) bit in the interrupt status register.
Timer Mode
In the timer mode a symmetrical square wave is generated whose
half period is equal in time to division of the selected counter/timer
clock frequency by the 16-bit number loaded in the CTLR CTUR.
Thus, the frequency of the counter/timer output will be equal to the
counter/timer clock frequency divided by twice the value of the
CTUR CTLR. While in the timer mode the ISR bit 3 (ISR[3]) will be
SC28C94
Product data sheet