ISP1507ABSTM STEricsson, ISP1507ABSTM Datasheet - Page 55

• Manufacturer Part Number: ISP1507ABSTM
• Manufacturer: STEricsson

Specifications of ISP1507ABSTM

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Pin Count: 32
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant

Table 34.
Table 35.
Table 36.
Table 37.
CD00222689
Product data sheet
Bit
2
1
0
Bit
Symbol
Reset
Access
Bit
7 to 5
4
3
2
1
0
Bit
Symbol
Reset
Access
Symbol
-
ID_GND
SESS_END
SESS_VALID
VBUS_VALID
HOST_DISCON
Symbol
SESS_VALID_F Session Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on
VBUS_VALID_F V
HOST_DISCON
_F
USB_INTR_EN_F_E - USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h,
S = 11h, C = 12h) bit description
USB_INTR_STAT - USB Interrupt Status register (address R = 13h) bit allocation
USB_INTR_STAT - USB Interrupt Status register (address R = 13h) bit description
USB_INTR_L - USB Interrupt Latch register (address R = 14h) bit allocation
10.1.7 USB_INTR_STAT register
10.1.8 USB_INTR_L register
R
R
X
7
7
0
This register (see
The bits of the USB_INTR_L register are automatically set by the ISP1507 when an
unmasked change occurs on the corresponding interrupt source signal. The ISP1507 will
automatically clear all bits when the link reads this register, or when the PHY enters
low-power or serial mode.
Remark: It is optional for the link to read this register when the clock is running because
all signal information will automatically be sent to the link through the RXCMD byte.
The bit allocation of this register is given in
Description
SESS_VLD.
A_VBUS_VLD.
Host Disconnect Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on
HOST_DISCON.
reserved
reserved
BUS
X
R
Description
reserved
ID Ground: Reflects the current value of the ID detector circuit.
Session End: Reflects the current value of the session end voltage comparator.
Session Valid: Reflects the current value of the session valid voltage comparator.
V
Host Disconnect: Reflects the current value of the host disconnect detector.
R
6
6
0
Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on
BUS
Valid: Reflects the current value of the V
Table
…continued
R
R
5
X
5
0
Rev. 04 — 20 May 2010
35) indicates the current value of the interrupt source signal.
ID_GND_L
ID_GND
R
R
4
0
4
0
SESS_END
SESS_
END_L
Table
R
R
3
0
3
0
ISP1507A; ISP1507B
BUS
37.
valid voltage comparator.
VALID_L
SESS_
SESS_
VALID
ULPI HS USB OTG transceiver
R
R
2
0
2
0
VALID_L
VBUS_
VBUS_
VALID
© ST-ERICSSON 2010. All rights reserved.
R
R
1
0
1
0
DISCON_L
DISCON
HOST_
HOST_
R
R
0
0
0
0
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