USB3320C-EZK Standard Microsystems (SMSC), USB3320C-EZK Datasheet - Page 50

• Manufacturer Part Number: USB3320C-EZK
• Description: USB PHY
• Manufacturer: Standard Microsystems (SMSC)

Specifications of USB3320C-EZK

• Lead Free Status / RoHS Status: Compliant

Revision 1.0 (07-14-09)
6.2.4.1
6.2.4.2
6.2.4.3
6.2.4.4
Several important functions for a device and host are designed into the transmitter blocks.
The USB3320 transmitter will transmit a 32-bit long high speed sync before every high speed packet.
In full and low speed modes a 8-bit sync is transmitted.
When the device or host needs to chirp for high speed port negotiation, the OpMode = 10b setting in
the
end of a chirp, the USB3320 OpMode bits should be changed only after the RXCMD linestate encoding
indicates that the transmitter has completed transmitting. Should the opmode be switched to normal
bit-stuffing and NRZI encoding before the transmit pipeline is empty, the remaining data in the pipeline
may be transmitted in an bit-stuff encoding format.
Please refer to the ULPI specification for a detailed discussion of USB reset and HS chirp.
High Speed Long EOP
When operating as a Hi-Speed host, the USB3320 will automatically generate a 40 bit long End of
Packet (EOP) after a SOF PID (A5h). The USB3320 determines when to send the 40-bit long EOP by
decoding the ULPI TXD CMD bits [3:0] for the SOF. The 40-bit long EOP is only transmitted when the
DpPulldown and DmPulldown bits in the
EOP is used to detect a disconnect in high speed mode.
In device mode, the USB3320 will not send a long EOP after a SOF PID.
Low Speed Keep-Alive
Low speed keep alive is supported by the USB3320. When in Low speed (XcvrSelect = 10b in the
Function Control
PID is received.
UTMI+ Level 3
Pre-amble is supported for UTMI+ Level 3 compatibility. When XcvrSelect = 11b in the
register in host mode (DpPulldown and DmPulldown both asserted), the USB3320 will pre-pend a full
speed pre-amble before the low speed packet. Full speed rise and fall times are used in this mode.
The pre-amble consists of the following: Full speed sync, the encoded pre-PID (C3h) and then full
speed idle (DP=1 and DM = 0). A low speed packet follows with a sync, data and a LS EOP.
The USB3320 will only support UTMI+ Level 3 as a host. The USB3320 does not support UTMI+ Level
3 as a peripheral. A UTMI+ Level 3 peripheral is an upstream hub port. The USB3320 will not decode
a pre-amble packet intended for a LS device when the USB3320 is configured as the upstream port
of a FS hub, XcvrSelect = 11b, DpPulldown = 0b, DmPulldown =0b.
Host Resume K
Resume K generation is supported by the USB3320. When the USB3320 exits the suspended (Low
Power Mode), the USB3320, when operating as a host, will transmit a K on DP/DM. The transmitters
will end the K with SE0 for two Low Speed bit times. If the USB3320 was operating in high speed
mode before the suspend, the host must change to high speed mode before the SE0 ends. SE0 is
two low speed bit times which is about 1.2 us. For more details please see sections 7.1.77 and 7.9 of
the USB Specification.
In device mode, the resume K will not append an SE0, but release the bus to the correct idle state,
depending upon the operational mode as shown in
The ULPI specification includes a detailed discussion of the resume sequence and the order of
operations required. To support Host start-up of less than 1mS the USB3320 implements the ULPI
AutoResume bit in the Interface Control register. The default AutoResume state is 0 and this bit should
be enabled for Host applications.
Function Control
register), the USB3320 will send out two Low speed bit times of SE0 when a SOF
register will turn off the bit-stuffing and NRZI encoding in the transmitter. At the
DATASHEET
OTG Control
50
Table
register are asserted. The Hi-Speed 40-bit long
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
5.1.
Function Control
SMSC USB3320
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