ISP1507DBSUM STEricsson, ISP1507DBSUM Datasheet - Page 49

• Manufacturer Part Number: ISP1507DBSUM
• Manufacturer: STEricsson

Specifications of ISP1507DBSUM

• Lead Free Status / RoHS Status: Compliant

Table 29.
Table 30.
Table 31.
Table 32.
CD00222690
Product data sheet
Bit
Symbol
Reset
Access
Bit
7 to 4
3
2
1
0
Bit
Symbol
Reset
Access
Bit
7 to 4
3
2
1
0
Symbol
-
SESS_END_F
SESS_VALID_F
VBUS_VALID_F
HOST_DISCON_F Host Disconnect Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on
Symbol
-
SESS_END_R
SESS_VALID_R
VBUS_VALID_R
HOST_DISCON_R Host Disconnect Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on
USB_INTR_EN_R_E - USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh, W = 0Dh,
S = 0Eh, C = 0Fh) bit allocation
USB_INTR_EN_R_E - USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh, W = 0Dh,
S = 0Eh, C = 0Fh) bit description
USB_INTR_EN_F_E - USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h,
S = 11h, C = 12h) bit allocation
USB_INTR_EN_F_E - USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h,
S = 11h, C = 12h) bit description
10.1.6 USB_INTR_EN_F_E register
R/W/S/C
R/W/S/C
7
0
7
0
The bits in this register enable interrupts and RXCMDs to be sent when the corresponding
bits in the USB_INTR_STAT register change from logic 1 to logic 0. By default, all
transitions are enabled. See
R/W/S/C
R/W/S/C
Description
reserved
Session End Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on
SESS_END.
Session Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on
SESS_VLD.
V
A_VBUS_VLD.
HOST_DISCON.
Description
reserved
Session End Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on
SESS_END.
Session Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on
SESS_VLD.
V
A_VBUS_VLD.
HOST_DISCON.
BUS
BUS
6
0
6
0
Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on
reserved
Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on
reserved
R/W/S/C
R/W/S/C
5
0
5
0
Rev. 04 — 20 May 2010
Table
R/W/S/C
R/W/S/C
4
1
4
1
31.
ULPI HS USB host and peripheral transceiver
R/W/S/C
R/W/S/C
END_R
END_F
SESS_
SESS_
3
1
3
1
ISP1507C; ISP1507D
VALID_R
VALID_F
R/W/S/C
R/W/S/C
SESS_
SESS_
2
1
2
1
VALID_R
R/W/S/C
VALID_F
R/W/S/C
VBUS_
VBUS_
© ST-ERICSSON 2010. All rights reserved.
1
1
1
1
DISCON_R
DISCON_F
R/W/S/C
R/W/S/C
HOST_
HOST_
0
1
0
1
49 of 73