ISP1301BS,118 NXP Semiconductors, ISP1301BS,118 Datasheet - Page 20

• Manufacturer Part Number: ISP1301BS,118
• Manufacturer: NXP Semiconductors

Specifications of ISP1301BS,118

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Operating Supply Voltage (typ): Not RequiredV
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): Not RequiredV
• Operating Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant

Table 21.
ISP1301_5
Product data sheet
Bit
Symbol
Reset
Access
OTG Control register: bit allocation
10.1.3.1 OTG Control register (Set/Clear: 06h/07h)
10.1.3 OTG registers
VBUS_
CHRG
R/S/C
7
0
Table 20.
Table 21
Table 22.
Bit
7
6
5
4 to 3
2
1
0
Bit
7
6
5
4
3
DISCHRG
VBUS_
R/S/C
Symbol
VBUS_CHRG
VBUS_DISCHRG
VBUS_DRV
ID_PULLDOWN
DM_PULLDOWN
6
0
provides the bit allocation of the OTG Control register.
Symbol
EN2V7
PSW_OE
AUDIO_EN
TRANSP_BDIR[1:0]
BI_DI
SPD_SUSP_CTRL
GLOBAL_PWR_DN
Mode Control 2 register: bit description
OTG Control register: bit description
VBUS_
R/S/C
DRV
5
0
Rev. 05 — 2 September 2009
discharge V
Description
charge V
drive V
connect the ID pin to ground
connect the DM pull-down resistor to ground
ID_PULL
DOWN
Description
0 — V
1 — V
Remark: For the operating condition to be USB compliant, it is
recommended to always set this bit as logic 0. Setting this bit as
logic 1 may not cause any functional problems, but it might cause
some USB specification violation in terms of voltage levels
required for the USB signals.
0 — ADR/PSW pin acts as an input
1 — ADR/PSW pin is driven
0 — SE receiver is enabled; cr_int detector is disabled
1 — SE receiver is turned off (pin VP = LOW, pin VM = LOW);
cr_int detector is enabled
controls the direction of data transfer in transparent
general-purpose buffer mode; see
0 — direction of DAT/VP and SE0/VM are fixed (transmit only)
1 — direction of DAT/VP and SE0/VM are controlled by
pin OE_N/INT_N; see
control of speed and suspend in USB modes:
0 — controlled by pins SPEED and SUSPEND
1 — controlled by bit SPEED_REG and bit SUSPEND_REG of
the Mode Control 1 register
0 — normal operation
1 — sets the ISP1301 to Power-down mode
Activities on the I
see
R/S/C
4
0
BUS
Section 11
BUS
CC
CC
to 5 V through the charge pump
BUS
through a resistor to 3.3 V
= 3.0 V to 4.5 V
= 2.7 V to 4.5 V
DM_PULL
through a resistor to ground
DOWN
R/S/C
3
1
2
C-bus or any OTG event can wake-up the chip;
Table 6
DP_PULL
DOWN
R/S/C
2
1
Table 8
DM_PULL
USB OTG transceiver
© ST-ERICSSON 2009. All rights reserved.
R/S/C
UP
1
0
ISP1301
DP_PULL
R/S/C
UP
0
0
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