ISP1301BS,118 NXP Semiconductors, ISP1301BS,118 Datasheet - Page 25

• Manufacturer Part Number: ISP1301BS,118
• Manufacturer: NXP Semiconductors

Specifications of ISP1301BS,118

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Operating Supply Voltage (typ): Not RequiredV
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): Not RequiredV
• Operating Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant

11. Clock wake-up scheme
ISP1301_5
Product data sheet
11.1 Power-down event
11.2 Clock wake-up events
The following subsections explain the ISP1301 clock stop timing, events triggering the
clock to wake up, and the timing of the clock wake-up.
The clock is stopped when the GLOBAL_PWR_DN bit is set. It takes approximately 8 ms
for the clock to stop from the time the power-down condition is detected. The clock always
stops at its falling edge. The waveform is given in
The clock wakes up when any of the following events occur on the ISP1301 pins:
The event triggers the clock to start and a stable clock is guaranteed after about six clock
periods, which is approximately 8 μs. The startup analog clock time is 10 μs. Therefore,
the total estimated start time after a triggered event is about 20 μs. The clock will always
start at its rising edge.
Waveforms of the clock wake-up because of different events are given in
Figure
Fig 7.
Fig 8.
•
•
•
•
•
•
GLOBAL_PWR_DN
SCL goes LOW.
V
SESS_VLD bit in the Interrupt Enable High register is set.
ID changes when mini-A plug is inserted, provided the ID_FLOAT bit in the Interrupt
Enable Low register is set.
ID changes when mini-A plug is removed, provided the ID_FLOAT bit in the Interrupt
Enable High register is set.
DP goes HIGH, provided the DP_HI bit in the Interrupt Enable High register is set.
DM goes HIGH, provided the DM_HI bit in the Interrupt Enable High register is set.
BUS
9,
Clock stopped using the GLOBAL_PWR_DN bit
Figure
Clock wake-up using SCL
goes above the session valid threshold (0.8 V to 2.0 V), provided the
CLOCK
SCL
10,
CLOCK
Figure 11
SCL
Rev. 05 — 2 September 2009
and
Figure
12.
20 μs
Figure
8 ms
7.
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USB OTG transceiver
© ST-ERICSSON 2009. All rights reserved.
ISP1301
Figure
004aaa217
8,
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