ISP1301BS,151 STEricsson, ISP1301BS,151 Datasheet - Page 23

• Manufacturer Part Number: ISP1301BS,151
• Manufacturer: STEricsson

Specifications of ISP1301BS,151

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Operating Supply Voltage (typ): Not RequiredV
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): Not RequiredV
• Operating Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 31.
ISP1301_5
Product data sheet
Bit
Symbol
Reset
Access
Interrupt Enable High register: bit allocation
10.1.4.4 Interrupt Enable High register (Set/Clear: 0Eh/0Fh)
CR_INT
10.2 Interrupts
R/S/C
7
0
Table 30.
The Interrupt Enable High register enables interrupts on transition from FALSE to TRUE.
Table 31
Table 32.
Table 26
Table 26
an interrupt has been generated, the OTG Controller should be able to read the status of
each signal and the bit that indicates whether that signal generated the interrupt.
A bit in the Interrupt Latch register is set when any of these occurs:
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
•
•
•
The corresponding bit in the Interrupt Enable High register is set, and the associated
signal changes from LOW to HIGH.
The corresponding bit in the Interrupt Enable Low register is set, and the associated
signal changes from HIGH to LOW.
Writing logic 1 to its set address causes the corresponding bit to be set.
BDIS_
ACON
R/S/C
Symbol
CR_INT
BDIS_ACON
ID_FLOAT
DM_HI
ID_GND
DP_HI
SESS_VLD
VBUS_VLD
Symbol
CR_INT
BDIS_ACON
ID_FLOAT
DM_HI
ID_GND
DP_HI
SESS_VLD
VBUS_VLD
6
0
provides the bit allocation of this register.
indicates the signals that can generate interrupts. Any of the signals given in
can generate an interrupt when the signal becomes either LOW or HIGH. After
Interrupt Enable Low register: bit description
Interrupt Enable High register: bit description
ID_FLOAT
R/S/C
5
0
Rev. 05 — 2 September 2009
Description
interrupt enable for CR_INT status change from 1 to 0
interrupt enable for BDIS_ACON status change from 1 to 0
interrupt enable for ID_FLOAT status change from 1 to 0
interrupt enable for DM_HI status change from 1 to 0
interrupt enable for ID_GND status change from 1 to 0
interrupt enable for DP_HI status change from 1 to 0
interrupt enable for SESS_VLD status change from 1 to 0
interrupt enable for VBUS_VLD status change from 1 to 0
Description
interrupt enable for CR_INT status change from 0 to 1
interrupt enable for BDIS_ACON status change from 0 to 1
interrupt enable for ID_FLOAT status change from 0 to 1
interrupt enable for DM_HI status change from 0 to 1
interrupt enable for ID_GND status change from 0 to 1
interrupt enable for DP_HI status change from 0 to 1
interrupt enable for SESS_VLD status change from 0 to 1
interrupt enable for VBUS_VLD status change from 0 to 1
DM_HI
R/S/C
4
0
ID_GND
R/S/C
3
0
DP_HI
R/S/C
2
0
SESS_VLD VBUS_VLD
USB OTG transceiver
© ST-ERICSSON 2009. All rights reserved.
R/S/C
1
0
ISP1301
R/S/C
0
0
23 of 49