SAF7118EHV1 NXP Semiconductors, SAF7118EHV1 Datasheet - Page 59
SAF7118EHV1
Manufacturer Part Number
SAF7118EHV1
Description
Manufacturer
NXP Semiconductors
Datasheet
1.SAF7118EHV1.pdf
(175 pages)
Specifications of SAF7118EHV1
Screening Level
Industrial
Package Type
HBGA
Pin Count
156
Lead Free Status / RoHS Status
Compliant
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NXP Semiconductors
SAF7118_4
Product data sheet
Table 13.
Table 14.
[1]
[2]
[3]
Input field under
processing
Upper input lines
Upper input lines
Lower input lines
Lower input lines
Detected input
field ID
0 = upper lines
0 = upper lines
1 = lower lines
1 = lower lines
Case 1: OFIDC[90h[6]] = 0; scaler input field ID as output ID; back-end interprets output field ID at logic 0
as upper output lines.
Case 2: OFIDC[90h[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 0 as
upper output lines.
Case 3: OFIDC[90h[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 1 as
upper output lines.
Examples for vertical phase offset usage: global equations
Vertical phase offset usage; assignment of the phase offsets
Output field
interpretation
upper output lines UP-UP
lower output lines
upper output lines LO-UP
lower output lines
Task
status
bit
0
1
0
1
Rev. 04 — 4 July 2008
Vertical phase
offset
YPY0[7:0] and
YPC0[7:0]
YPY1[7:0] and
YPC1[7:0]
YPY2[7:0] and
YPC2[7:0]
YPY3[7:0] and
YPC3[7:0]
Multistandard video decoder with adaptive comb filter
Used
abbreviation
UP-LO
LO-LO
Case
case 1
case 2
case 3
case 1
case 2
case 3
case 1
case 2
case 3
case 1
case 2
case 3
[1]
[2]
[3]
Equation for phase offset
calculation (decimal values)
PHO + 16
PHO
Equation to be used
UP-UP (PHO)
UP-UP
UP-LO
UP-UP (PHO)
UP-LO
UP-UP
LO-LO
LO-UP
LO-LO
LO-LO
LO-LO
LO-UP
PHO
PHO
+
+
YSCY[15:0]
---------------------------- -
YSCY[15:0]
---------------------------- -
PHO
PHO
64
64
+
+
YSCY[15:0]
---------------------------- - 16
YSCY[15:0]
---------------------------- - 16
SAF7118
© NXP B.V. 2008. All rights reserved.
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