SAA7118EEB-T NXP Semiconductors, SAA7118EEB-T Datasheet - Page 131

• Manufacturer Part Number: SAA7118EEB-T
• Description: Video ICs COMPONENT VID DECODER W/COMB F
• Manufacturer: NXP Semiconductors
• Type: Multi-Standard Video Decoderr

Specifications of SAA7118EEB-T

• Adc/dac Resolution: 9b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-700
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Not Compliant
• Other names: SAA7118E/V1,518

NXP Semiconductors
Table 102. I port FIFO flag control and arbitration; global set 86h[3:0]
[1]
Table 103. I port I/O enable, output clock and gated clock phase control; global set 87h[7:4]
[1]
[2]
Table 104. I port I/O enable, output clock and gated clock phase control; global set 87h[1:0]
SAA7118_7
Product data sheet
I port FIFO flag control and arbitration
FAE FIFO flag almost empty level
FAF FIFO flag almost full level
Output clock and gated clock phase control
ICLK default output phase
ICLK phase shifted by
ICKS0 = 0 (subaddress 80h)
ICLK phase shifted by approximately 3 ns
ICLK phase shifted by
3 ns
IDQ = gated clock default output phase
IDQ = gated clock phase shifted by
gated clock output
IDQ = gated clock phase shifted by approximately 3 ns
IDQ = gated clock phase shifted by
3 ns
I port I/O enable
I port output is disabled by software
I port output is enabled by software
I port output is enabled by pin ITRI at logic 0
I port output is enabled by pin ITRI at logic 1
< 16 double words
< 8 double words
< 4 double words
0 double words
32 double words
X = don’t care.
X = don’t care.
IPCK3 and IPCK2 only affect the gated clock (subaddress 80h, bit ICKS2 = 1).
16 double words
24 double words
28 double words
alternatively to setting ‘01’
alternatively to setting ‘01’
1
1
2
2
clock cycle
clock cycle + approximately
1
1
2
2
clock cycle
clock cycle + approximately
recommended for ICKS1 = 1 and
Rev. 07 — 7 July 2008
recommended for
Multistandard video decoder with adaptive comb filter
[1]
Control bits D3 to D0
FFL1
X
X
X
X
0
0
1
1
Control bits D7 to D4
IPCK3
X
X
X
X
0
0
1
1
Control bits D1 and D0
IPE1
0
0
1
1
[2]
FFL0
X
X
X
X
0
1
0
1
IPCK2
X
X
X
X
0
1
0
1
[2]
[1]
IPE0
0
1
0
1
FEL1
0
0
1
1
X
X
X
X
IPCK1
0
0
1
1
X
X
X
X
SAA7118
© NXP B.V. 2008. All rights reserved.
FEL0
0
1
0
1
X
X
X
X
IPCK0
0
1
0
1
X
X
X
X
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